Simulation Results: rv_timer

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.32 %
  • code
  • 95.85 %
  • assert
  • 96.52 %
  • func
  • 99.58 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 124.860us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 73.496us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 18.611us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 891.161us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 150.349us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 42.588us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 18.611us 1 1 100.00
rv_timer_csr_aliasing 2.000s 150.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.000s 141.969us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 3.000s 4210.814us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 39.000s 41019.158us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 39.000s 41019.158us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.000s 1763.923us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 16.326us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 2.000s 59.751us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 3.000s 1573.699us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 3.000s 1573.699us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 73.496us 1 1 100.00
rv_timer_csr_rw 1.000s 18.611us 1 1 100.00
rv_timer_csr_aliasing 2.000s 150.349us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 160.640us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 73.496us 1 1 100.00
rv_timer_csr_rw 1.000s 18.611us 1 1 100.00
rv_timer_csr_aliasing 2.000s 150.349us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 160.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 60.982us 1 1 100.00
rv_timer_tl_intg_err 1.000s 172.293us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 172.293us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 133.823us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 371.032us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 13.000s 3594.900us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 91155944539464911714356307595890518699562650312235010340318071084734902513789 84
UVM_INFO @ 133822613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 25614738083129290616854930543490740651916852777400079829329374805661672875257 84
UVM_INFO @ 141969388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 70607680565548239234699158381160923256751873509387292340275946871723319620028 85
UVM_INFO @ 371032113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---