Simulation Results: sram_ctrl/main

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.30 %
  • code
  • 95.78 %
  • assert
  • 98.10 %
  • func
  • 95.00 %
  • block
  • 96.03 %
  • line
  • 96.75 %
  • branch
  • 94.17 %
  • toggle
  • 92.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 1941.666us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 36.716us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.505us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 202.897us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.285us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 346.907us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 17.505us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.285us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 196.000s 8440.448us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 76.000s 3026.944us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 15.000s 7219.561us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 120.000s 32012.968us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 119.000s 10951.146us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 12.000s 5319.771us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 27.000s 34309.827us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 16.000s 16225.562us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 6.000s 718.781us 1 1 100.00
sram_ctrl_partial_access_b2b 225.000s 64162.832us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 6.000s 2752.450us 0 1 0.00
sram_ctrl_throughput_w_partial_write 4.000s 2752.867us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 2553.384us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 13.000s 4271.569us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 465.819us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 209.000s 96345.060us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 38.995us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 161.421us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 161.421us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 36.716us 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.505us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.285us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 120.891us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 36.716us 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.505us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 47.285us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 120.891us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 21.000s 8780.678us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 316.606us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 2486.162us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 316.606us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 2486.162us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 4271.569us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 4271.569us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.505us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 16.000s 16225.562us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 16.000s 16225.562us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 16.000s 16225.562us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 27.000s 34309.827us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 671.585us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 21.000s 8780.678us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 2304.289us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1941.666us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1941.666us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 16.000s 16225.562us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 316.606us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 27.000s 34309.827us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 316.606us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 316.606us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 1941.666us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 316.606us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 33.000s 7285.459us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 66336830640850708246594941338681863887416261655328514144562195049937672507222 86
UVM_INFO @ 2752449644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 4697536465005005983747618052643791510722875009481742244470774712585174195974 86
UVM_INFO @ 2752867487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 31768680376212301859479212652976391670149060744848262666404253076949148410842 86
UVM_INFO @ 2553384310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---