Simulation Results: sram_ctrl/ret

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.72 %
  • code
  • 82.08 %
  • assert
  • 97.67 %
  • func
  • 95.40 %
  • block
  • 93.42 %
  • line
  • 94.61 %
  • branch
  • 88.73 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 366.456us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 37.824us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 3.000s 46.444us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 104.042us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.160us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 75.089us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 3.000s 46.444us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.160us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.000s 2058.474us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 235.190us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 9.000s 796.890us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 179.000s 13898.806us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 7.000s 2408.472us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 18.000s 2557.374us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 611.794us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 4.000s 120.850us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 236.024us 1 1 100.00
sram_ctrl_partial_access_b2b 224.000s 17105.317us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 33.324us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 71.406us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 29.446us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 161.029us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 87.509us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 16.000s 7455.682us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 12.779us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 125.969us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 125.969us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 37.824us 1 1 100.00
sram_ctrl_csr_rw 3.000s 46.444us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.160us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 92.592us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 37.824us 1 1 100.00
sram_ctrl_csr_rw 3.000s 46.444us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 28.160us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 92.592us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 234.352us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1108.688us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 472.118us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1108.688us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 472.118us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 161.029us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 161.029us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 3.000s 46.444us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 4.000s 120.850us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 4.000s 120.850us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 4.000s 120.850us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 611.794us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 160.293us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 234.352us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 198.296us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 366.456us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 366.456us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 4.000s 120.850us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1108.688us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 611.794us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1108.688us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1108.688us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 366.456us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1108.688us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 78.000s 2384.593us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 57552428211756765887677659587348187855505164366393149432765704972041800733303 86
UVM_INFO @ 33324393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 32282953023338594089313012459618794616247754243640094016381409744830655206364 86
UVM_INFO @ 71405576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 29828279345715460536285761065611788757077101391780386996353175216375768753457 86
UVM_INFO @ 29446366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---