Simulation Results

Simulation Results: uart

22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.88 %

code
92.69 %

assert
98.27 %

func
90.69 %

block
99.08 %

line
99.52 %

branch
98.34 %

toggle
72.91 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		95.45%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	5.000s	5811.470us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	1.000s	52.988us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	1.000s	13.317us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	3.000s	581.405us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	1.000s	38.468us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	1.000s	93.563us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	1.000s	13.317us	1	1	100.00
	uart_csr_aliasing	1.000s	38.468us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	89.000s	177235.859us	1	1	100.00
parity				2	2	100.00
	uart_smoke	5.000s	5811.470us	1	1	100.00
	uart_tx_rx	89.000s	177235.859us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	16.000s	48609.587us	1	1	100.00
	uart_rx_parity_err	74.000s	118698.949us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	89.000s	177235.859us	1	1	100.00
	uart_intr	16.000s	48609.587us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	54.000s	166483.161us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	95.000s	83304.443us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	37.000s	25492.446us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	16.000s	48609.587us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	16.000s	48609.587us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	16.000s	48609.587us	1	1	100.00
perf				1	1	100.00
	uart_perf	87.000s	4397.114us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	5.000s	4593.499us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	5.000s	4593.499us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	3.000s	249.277us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	3.000s	450.180us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	3.000s	1494.151us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	22.000s	4955.796us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	474.000s	118938.975us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	179.000s	198949.901us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	1.000s	43.586us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	1.000s	39.257us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	3.000s	54.057us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	3.000s	54.057us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	1.000s	52.988us	1	1	100.00
	uart_csr_rw	1.000s	13.317us	1	1	100.00
	uart_csr_aliasing	1.000s	38.468us	1	1	100.00
	uart_same_csr_outstanding	2.000s	37.197us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	1.000s	52.988us	1	1	100.00
	uart_csr_rw	1.000s	13.317us	1	1	100.00
	uart_csr_aliasing	1.000s	38.468us	1	1	100.00
	uart_same_csr_outstanding	2.000s	37.197us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	1.000s	39.591us	1	1	100.00
	uart_tl_intg_err	2.000s	52.322us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	2.000s	52.322us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	17.000s	2972.357us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				1 test run
	uart_noise_filter	78501616477674283238110124333856685252902581790609228928932026665842880193875	83	UVM_ERROR @ 246226769 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 246226769 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 246286769 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 246286769 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0