Simulation Results: ac_range_check

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.79 %
  • code
  • 93.06 %
  • assert
  • 97.75 %
  • func
  • 57.56 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.00 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 25.000s 5965.618us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 42.000s 5401.244us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 3.000s 33.587us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 19.371us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 31.000s 10969.074us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 20.000s 2665.768us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 29.803us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 19.371us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 2665.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 30.041us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 29.000s 1663.599us 1 1 100.00
stress_all 0 1 0.00
ac_range_check_stress_all 82.000s 18031.471us 0 1 0.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 47.958us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 39.419us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 62.503us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 62.503us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 3.000s 33.587us 1 1 100.00
ac_range_check_csr_rw 2.000s 19.371us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 2665.768us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 378.509us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 3.000s 33.587us 1 1 100.00
ac_range_check_csr_rw 2.000s 19.371us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 2665.768us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 378.509us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 9339.150us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 9339.150us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 9339.150us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 9339.150us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 79.000s 4759.775us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 39.931us 1 1 100.00
ac_range_check_tl_intg_err 9.000s 1617.090us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 225.000s 2153.736us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 28.000s 1531.476us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 1 test run
ac_range_check_stress_all 34681819018481623594563521149513130395389200126758053741800889544009086873145 9376
UVM_INFO @ 18031470649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---