Simulation Results: aes/gcm_masked

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.95 %
  • code
  • 95.14 %
  • assert
  • 98.43 %
  • func
  • 67.28 %
  • block
  • 95.77 %
  • line
  • 97.53 %
  • branch
  • 89.48 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
94.74%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 85.602us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 103.544us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 83.230us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 83.881us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 464.183us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 94.940us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 144.994us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 83.881us 1 1 100.00
aes_csr_aliasing 2.000s 94.940us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 103.544us 1 1 100.00
aes_config_error 3.000s 243.339us 1 1 100.00
aes_stress 2.000s 134.283us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 103.544us 1 1 100.00
aes_config_error 3.000s 243.339us 1 1 100.00
aes_stress 2.000s 134.283us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 134.283us 1 1 100.00
aes_b2b 10.000s 1210.671us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 134.283us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 103.544us 1 1 100.00
aes_config_error 3.000s 243.339us 1 1 100.00
aes_stress 2.000s 134.283us 1 1 100.00
aes_alert_reset 5.000s 257.157us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 106.963us 1 1 100.00
aes_config_error 3.000s 243.339us 1 1 100.00
aes_alert_reset 5.000s 257.157us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 103.287us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 9.000s 461.436us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 873.784us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 5.000s 257.157us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 134.283us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 134.283us 1 1 100.00
aes_sideload 3.000s 196.696us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 5.000s 226.269us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 11.000s 277.825us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 4.000s 344.393us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 99.087us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 405.619us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 405.619us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 83.230us 1 1 100.00
aes_csr_rw 1.000s 83.881us 1 1 100.00
aes_csr_aliasing 2.000s 94.940us 1 1 100.00
aes_same_csr_outstanding 2.000s 83.901us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 83.230us 1 1 100.00
aes_csr_rw 1.000s 83.881us 1 1 100.00
aes_csr_aliasing 2.000s 94.940us 1 1 100.00
aes_same_csr_outstanding 2.000s 83.901us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 59.953us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 10.545us 0 1 0.00
aes_control_fi 3.000s 49.856us 1 1 100.00
aes_cipher_fi 2.000s 84.245us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 89.199us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 89.199us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 89.199us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 89.199us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 702.115us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 963.014us 1 1 100.00
aes_tl_intg_err 2.000s 90.496us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 90.496us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 5.000s 257.157us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 89.199us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 89.199us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 103.544us 1 1 100.00
aes_stress 2.000s 134.283us 1 1 100.00
aes_alert_reset 5.000s 257.157us 1 1 100.00
aes_core_fi 2.000s 86.974us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 4.000s 344.393us 1 1 100.00
aes_config_error 3.000s 243.339us 1 1 100.00
aes_stress 2.000s 134.283us 1 1 100.00
aes_core_fi 2.000s 86.974us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 89.199us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 135.951us 1 1 100.00
aes_stress 2.000s 134.283us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 134.283us 1 1 100.00
aes_sideload 3.000s 196.696us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 135.951us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 135.951us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 135.951us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 135.951us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 135.951us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 134.283us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 134.283us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 10.545us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 10.545us 0 1 0.00
aes_control_fi 3.000s 49.856us 1 1 100.00
aes_cipher_fi 2.000s 84.245us 1 1 100.00
aes_ctr_fi 3.000s 71.582us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 10.545us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 10.545us 0 1 0.00
aes_control_fi 3.000s 49.856us 1 1 100.00
aes_cipher_fi 2.000s 84.245us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 84.245us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 10.545us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 10.545us 0 1 0.00
aes_control_fi 3.000s 49.856us 1 1 100.00
aes_ctr_fi 3.000s 71.582us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 10.545us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 10.545us 0 1 0.00
aes_control_fi 3.000s 49.856us 1 1 100.00
aes_cipher_fi 2.000s 84.245us 1 1 100.00
aes_ctr_fi 3.000s 71.582us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 5.000s 257.157us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 10.545us 0 1 0.00
aes_control_fi 3.000s 49.856us 1 1 100.00
aes_cipher_fi 2.000s 84.245us 1 1 100.00
aes_ctr_fi 3.000s 71.582us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 10.545us 0 1 0.00
aes_control_fi 3.000s 49.856us 1 1 100.00
aes_cipher_fi 2.000s 84.245us 1 1 100.00
aes_ctr_fi 3.000s 71.582us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 10.545us 0 1 0.00
aes_control_fi 3.000s 49.856us 1 1 100.00
aes_ctr_fi 3.000s 71.582us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 2.000s 71.573us 1 1 100.00
aes_fi 2.000s 10.545us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 10.545us 0 1 0.00
aes_control_fi 3.000s 49.856us 1 1 100.00
aes_cipher_fi 2.000s 84.245us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 17.000s 1667.956us 0 1 0.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1137): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) 1 test run
aes_fi 8979563103795935704982466859977551145515886265173351938150452447215310631510 2466
UVM_ERROR @ 10544649 ps: (aes_core.sv:1137) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
UVM_INFO @ 10544649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 1 test run
aes_stress_all 73737184233032916575103466219468991878636289511831720625907890321034531483563 65049
TEST FAILED MESSAGES DID NOT MATCH
0 d3 da da 0
1 00 ae ae 0
UVM_FATAL (aes_base_vseq.sv:322) virtual_sequencer [aes_stress_vseq] Expected GCM phase GCM_AAD, got GCM_TEXT 1 test run
aes_stress_all_with_rand_reset 16934122461794657502254508608117257197016683061579606217462413111403517962312 426
UVM_INFO @ 1667956437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---