Simulation Results: alert_handler

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.10 %
  • code
  • 90.59 %
  • assert
  • 98.02 %
  • func
  • 75.69 %
  • line
  • 99.75 %
  • branch
  • 98.16 %
  • cond
  • 90.11 %
  • toggle
  • 85.90 %
  • FSM
  • 79.03 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 19.140s 1880.202us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.030s 63.042us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 2.980s 134.555us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 222.010s 12020.918us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 102.650s 1435.068us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.240s 135.729us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 2.980s 134.555us 1 1 100.00
alert_handler_csr_aliasing 102.650s 1435.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 216.160s 8036.505us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 52.710s 6111.762us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1249.250s 22209.159us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 18.580s 1177.841us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 19.140s 1880.202us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 55.660s 2539.231us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 24.310s 344.453us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 215.960s 7807.578us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 858.090s 56617.539us 1 1 100.00
alert_handler_lpg_stub_clk 1302.790s 18353.929us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1701.260s 108477.748us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 5.850s 792.134us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.600s 23.103us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.950s 8.349us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 7.150s 987.315us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 7.150s 987.315us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.030s 63.042us 1 1 100.00
alert_handler_csr_rw 2.980s 134.555us 1 1 100.00
alert_handler_csr_aliasing 102.650s 1435.068us 1 1 100.00
alert_handler_same_csr_outstanding 8.770s 101.504us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.030s 63.042us 1 1 100.00
alert_handler_csr_rw 2.980s 134.555us 1 1 100.00
alert_handler_csr_aliasing 102.650s 1435.068us 1 1 100.00
alert_handler_same_csr_outstanding 8.770s 101.504us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 75.660s 3903.175us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 75.660s 3903.175us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 75.660s 3903.175us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 75.660s 3903.175us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 1030.060s 18365.942us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 10.290s 3350.252us 1 1 100.00
alert_handler_tl_intg_err 2.500s 69.155us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.500s 69.155us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 75.660s 3903.175us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 19.140s 1880.202us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 19.140s 1880.202us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 19.140s 1880.202us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 19.140s 1880.202us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 18.580s 1177.841us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 858.090s 56617.539us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 18.580s 1177.841us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1249.250s 22209.159us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1249.250s 22209.159us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 10.290s 3350.252us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 10.290s 3350.252us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 10.290s 3350.252us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 10.290s 3350.252us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 10.290s 3350.252us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.290s 3350.252us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.290s 3350.252us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.290s 3350.252us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 10.290s 3350.252us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 71.880s 11669.680us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 82064354961702198016465394972135080542784062461102933398107081565973636456111 196
UVM_INFO @ 792134314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 46561583767260049047819781784469653913244619528654092323695700724674923135400 125
UVM_INFO @ 11669680489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---