Simulation Results: clkmgr

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.55 %
  • code
  • 68.48 %
  • assert
  • 89.05 %
  • func
  • 69.11 %
  • line
  • 81.61 %
  • branch
  • 86.53 %
  • cond
  • 77.56 %
  • toggle
  • 96.70 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.160s 56.601us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.070s 51.618us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.690s 2.112us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 2.780s 152.534us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.450s 87.385us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.560s 76.111us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.690s 2.112us 0 1 0.00
clkmgr_csr_aliasing 1.450s 87.385us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.850s 25.469us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.910s 88.560us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.860s 15.557us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.160s 56.601us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.730s 9.618us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.730s 3.171us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.730s 9.618us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 3.110s 310.440us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.020s 30.257us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.940s 42.190us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.940s 42.190us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 1.070s 51.618us 1 1 100.00
clkmgr_csr_rw 0.690s 2.112us 0 1 0.00
clkmgr_csr_aliasing 1.450s 87.385us 1 1 100.00
clkmgr_same_csr_outstanding 0.650s 7.582us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 1.070s 51.618us 1 1 100.00
clkmgr_csr_rw 0.690s 2.112us 0 1 0.00
clkmgr_csr_aliasing 1.450s 87.385us 1 1 100.00
clkmgr_same_csr_outstanding 0.650s 7.582us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 0.630s 4.404us 0 1 0.00
clkmgr_tl_intg_err 0.620s 2.195us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.550s 233.069us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.550s 233.069us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.550s 233.069us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.550s 233.069us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.620s 6.566us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.620s 2.195us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.730s 9.618us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.730s 3.171us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.550s 233.069us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.900s 23.966us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.690s 2.112us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.630s 4.404us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.690s 2.112us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.690s 2.112us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.630s 4.404us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.720s 5.603us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 4.250s 362.428us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 49168998810349671975714524879985651312545926386655757582053953431709398323516 76
UVM_INFO @ 9618026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 81403418583001991338447350845716792858826309483183575970018537349286262608572 152
UVM_INFO @ 310439609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 7841442275534421456221702378016360384540542923552076151498567801647478584992 78
UVM_INFO @ 3170668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 102139675672340711869985459095013931983594955143420980249134735853605406689681 183
UVM_INFO @ 362427590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 70498649380029195521618305092276151516754532890742813749743710620709651781084 75
UVM_INFO @ 6565816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 67488919607503144641790989503955209852047892775710074409854188041122159397434 75
UVM_INFO @ 2112418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 2 test runs
clkmgr_tl_intg_err 2831543741094858608677480136737646643115122102724397143674161968647656340556 75
UVM_INFO @ 2194738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 43468751798849011633185665781294467427987963334299488166590869342110343000917 76
UVM_INFO @ 76111127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 77041400111827558177534007875934274189408065619354785209924830339866900509518 74
UVM_INFO @ 5603181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 108481946258679689434696686862538219809455596054757937967819762377609580325535 80
UVM_INFO @ 4403901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 19855316330406532080784476237401982302912482663932062981238978565770284626890 75
UVM_INFO @ 152533702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 60286363306507319656307609936693602052960216855658491190790251348034433830331 75
UVM_INFO @ 7582335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---