Simulation Results: csrng

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 79.39 %
  • code
  • 90.38 %
  • assert
  • 94.10 %
  • func
  • 53.69 %
  • block
  • 95.45 %
  • line
  • 96.24 %
  • branch
  • 89.23 %
  • toggle
  • 90.33 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 47.192us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 28.520us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 68.036us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 14.000s 661.907us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 75.686us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 206.862us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 68.036us 1 1 100.00
csrng_csr_aliasing 3.000s 75.686us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 164.921us 1 1 100.00
alerts 1 1 100.00
csrng_alert 7.000s 182.780us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 88.158us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 5.000s 76.226us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 5.000s 76.226us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 6.000s 260.389us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 23.890us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 38.660us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 5.000s 234.108us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 5.000s 234.108us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 28.520us 1 1 100.00
csrng_csr_rw 2.000s 68.036us 1 1 100.00
csrng_csr_aliasing 3.000s 75.686us 1 1 100.00
csrng_same_csr_outstanding 3.000s 95.853us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 28.520us 1 1 100.00
csrng_csr_rw 2.000s 68.036us 1 1 100.00
csrng_csr_aliasing 3.000s 75.686us 1 1 100.00
csrng_same_csr_outstanding 3.000s 95.853us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 71.074us 1 1 100.00
csrng_tl_intg_err 3.000s 64.361us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 1.000s 10.241us 0 1 0.00
csrng_csr_rw 2.000s 68.036us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 7.000s 182.780us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 6.000s 260.389us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 164.921us 1 1 100.00
csrng_err 3.000s 88.158us 1 1 100.00
csrng_sec_cm 3.000s 71.074us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 164.921us 1 1 100.00
csrng_err 3.000s 88.158us 1 1 100.00
csrng_sec_cm 3.000s 71.074us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 164.921us 1 1 100.00
csrng_err 3.000s 88.158us 1 1 100.00
csrng_sec_cm 3.000s 71.074us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 164.921us 1 1 100.00
csrng_err 3.000s 88.158us 1 1 100.00
csrng_sec_cm 3.000s 71.074us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 164.921us 1 1 100.00
csrng_err 3.000s 88.158us 1 1 100.00
csrng_sec_cm 3.000s 71.074us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 7.000s 182.780us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 164.921us 1 1 100.00
csrng_err 3.000s 88.158us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 6.000s 260.389us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 7.000s 182.780us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 64.361us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 164.921us 1 1 100.00
csrng_err 3.000s 88.158us 1 1 100.00
csrng_sec_cm 3.000s 71.074us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 164.921us 1 1 100.00
csrng_err 3.000s 88.158us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 164.921us 1 1 100.00
csrng_err 3.000s 88.158us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 164.921us 1 1 100.00
csrng_err 3.000s 88.158us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 164.921us 1 1 100.00
csrng_err 3.000s 88.158us 1 1 100.00
csrng_sec_cm 3.000s 71.074us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 164.921us 1 1 100.00
csrng_err 3.000s 88.158us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 76523310537143864901668900308923019034091380503789822511525039689537703899234 100
UVM_INFO @ 76225551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 1 test run
csrng_regwen 112066474882048295954774875076646327631752621592328149261613045510189275232995 99
UVM_INFO @ 10240917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 43550636362613563281061564218732241301846634767963147826189865858489071221954 None