Simulation Results: dma

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.86 %
  • code
  • 90.03 %
  • assert
  • 96.50 %
  • func
  • 62.04 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 90.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 275.313us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 307.561us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 287.573us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 52.958us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 100.744us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 9.000s 859.944us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 5.000s 158.661us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 66.183us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 100.744us 1 1 100.00
dma_csr_aliasing 5.000s 158.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 33.000s 36858.741us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 175.000s 74197.964us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 314.000s 34551.374us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 314.000s 34551.374us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 175.000s 74197.964us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 819.000s 140888.767us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 314.000s 34551.374us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 5.000s 826.277us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 95.000s 29772.958us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 12.741us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 12.970us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 187.828us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 187.828us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 52.958us 1 1 100.00
dma_csr_rw 2.000s 100.744us 1 1 100.00
dma_csr_aliasing 5.000s 158.661us 1 1 100.00
dma_same_csr_outstanding 2.000s 477.974us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 52.958us 1 1 100.00
dma_csr_rw 2.000s 100.744us 1 1 100.00
dma_csr_aliasing 5.000s 158.661us 1 1 100.00
dma_same_csr_outstanding 2.000s 477.974us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 22.000s 233.581us 1 1 100.00
dma_generic_stress 819.000s 140888.767us 1 1 100.00
dma_handshake_stress 314.000s 34551.374us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 8.000s 1946.658us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 51.670us 1 1 100.00
dma_sec_cm 1.000s 49.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 110.000s 36687.153us 1 1 100.00
dma_longer_transfer 3.000s 89.572us 1 1 100.00
dma_stress_all_with_rand_reset 16.000s 20213.660us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 18433625184135699752279783165345319344564281467199803599392477806346194380298 112
UVM_INFO @ 20213659963ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---