Simulation Results: edn/edn0

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.98 %
  • code
  • 83.35 %
  • assert
  • 95.35 %
  • func
  • 49.23 %
  • block
  • 93.73 %
  • line
  • 96.64 %
  • branch
  • 86.46 %
  • toggle
  • 72.79 %
  • FSM
  • 77.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 17.588us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 13.742us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 25.116us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 658.370us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 82.415us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 77.096us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 25.116us 1 1 100.00
edn_csr_aliasing 2.000s 82.415us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 86.794us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 86.794us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 86.794us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 30.267us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 48.365us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 30.290us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 33.736us 1 1 100.00
edn_disable_auto_req_mode 2.000s 25.555us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.000s 206.349us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 36.076us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 20.307us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 38.472us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 38.472us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 13.742us 1 1 100.00
edn_csr_rw 1.000s 25.116us 1 1 100.00
edn_csr_aliasing 2.000s 82.415us 1 1 100.00
edn_same_csr_outstanding 2.000s 39.861us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 13.742us 1 1 100.00
edn_csr_rw 1.000s 25.116us 1 1 100.00
edn_csr_aliasing 2.000s 82.415us 1 1 100.00
edn_same_csr_outstanding 2.000s 39.861us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.000s 1184.492us 1 1 100.00
edn_tl_intg_err 2.000s 128.681us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 45.602us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 48.365us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 1184.492us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 1184.492us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 1184.492us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 1184.492us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 48.365us 1 1 100.00
edn_sec_cm 5.000s 1184.492us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 48.365us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 128.681us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 59.000s 3227.025us 1 1 100.00