Simulation Results: edn/edn1

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.85 %
  • code
  • 84.45 %
  • assert
  • 98.44 %
  • func
  • 80.67 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 89.77 %
  • toggle
  • 95.57 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.830s 51.005us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.020s 36.166us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.840s 14.765us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.820s 621.116us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.300s 44.218us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.360s 24.420us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.840s 14.765us 1 1 100.00
edn_csr_aliasing 1.300s 44.218us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.210s 59.583us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.210s 59.583us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.210s 59.583us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.760s 59.630us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.400s 314.230us 1 1 100.00
errs 1 1 100.00
edn_err 0.840s 40.104us 1 1 100.00
disable 2 2 100.00
edn_disable 0.940s 30.172us 1 1 100.00
edn_disable_auto_req_mode 1.120s 80.470us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.740s 305.158us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 15.312us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.870s 214.354us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.950s 216.723us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.950s 216.723us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.020s 36.166us 1 1 100.00
edn_csr_rw 0.840s 14.765us 1 1 100.00
edn_csr_aliasing 1.300s 44.218us 1 1 100.00
edn_same_csr_outstanding 1.100s 57.940us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.020s 36.166us 1 1 100.00
edn_csr_rw 0.840s 14.765us 1 1 100.00
edn_csr_aliasing 1.300s 44.218us 1 1 100.00
edn_same_csr_outstanding 1.100s 57.940us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.110s 152.389us 1 1 100.00
edn_tl_intg_err 1.270s 184.028us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.880s 19.411us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.400s 314.230us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.110s 152.389us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.110s 152.389us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.110s 152.389us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.110s 152.389us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.400s 314.230us 1 1 100.00
edn_sec_cm 2.110s 152.389us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.400s 314.230us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.270s 184.028us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 58.390s 14367.874us 1 1 100.00