Simulation Results: entropy_src/rng_16bits

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 69.48 %
  • code
  • 81.95 %
  • assert
  • 74.20 %
  • func
  • 52.30 %
  • block
  • 94.08 %
  • line
  • 97.75 %
  • branch
  • 86.00 %
  • toggle
  • 52.38 %
  • FSM
  • 91.67 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 248.027us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 29.175us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 99.824us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 8.000s 222.963us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 65.047us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 12.338us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 99.824us 1 1 100.00
entropy_src_csr_aliasing 3.000s 65.047us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 3.000s 248.027us 1 1 100.00
entropy_src_rng 326.000s 13040.825us 1 1 100.00
entropy_src_fw_ov 78.000s 14305.354us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 78.000s 14305.354us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 326.000s 13040.825us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 333.000s 14024.064us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 326.000s 13040.825us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 326.000s 13040.825us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 326.000s 13040.825us 1 1 100.00
entropy_src_intr 12.000s 2827.087us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 326.000s 13040.825us 1 1 100.00
entropy_src_functional_alerts 5.000s 599.099us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 296.000s 13144.271us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 30.267us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 15.000s 344.287us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 41.604us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 17.497us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 530.359us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 530.359us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 29.175us 1 1 100.00
entropy_src_csr_rw 2.000s 99.824us 1 1 100.00
entropy_src_csr_aliasing 3.000s 65.047us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 26.279us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 29.175us 1 1 100.00
entropy_src_csr_rw 2.000s 99.824us 1 1 100.00
entropy_src_csr_aliasing 3.000s 65.047us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 26.279us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 59.062us 1 1 100.00
entropy_src_tl_intg_err 3.000s 65.854us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 326.000s 13040.825us 1 1 100.00
entropy_src_cfg_regwen 2.000s 42.485us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 326.000s 13040.825us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 326.000s 13040.825us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 326.000s 13040.825us 1 1 100.00
entropy_src_fw_ov 78.000s 14305.354us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 30.267us 1 1 100.00
entropy_src_sec_cm 2.000s 59.062us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 30.267us 1 1 100.00
entropy_src_sec_cm 2.000s 59.062us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 326.000s 13040.825us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 30.267us 1 1 100.00
entropy_src_sec_cm 2.000s 59.062us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 30.267us 1 1 100.00
entropy_src_sec_cm 2.000s 59.062us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 30.267us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 599.099us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 65.854us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 165.000s 14047.391us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 21.000s 3375.846us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold 1 test run
entropy_src_stress_all_with_rand_reset 90460458083214235991539543016959858505853689912705681897615965195061957644880 628
UVM_INFO @ 3375845658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror alert_fail_counts 1 test run
entropy_src_csr_mem_rw_with_rand_reset 26284214760235737687104875241725348764591868251335746037269625369328301867518 113
UVM_INFO @ 12338186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---