| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 4 | 4 | 100.00 | |||
| gpio_smoke | 0.780s | 50.379us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 1.200s | 84.423us | 1 | 1 | 100.00 | |
| gpio_smoke_en_cdc_prim | 1.280s | 122.346us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.240s | 377.640us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 0.660s | 49.360us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| gpio_csr_rw | 0.750s | 81.165us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 7.260s | 597.451us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 1.240s | 77.551us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 0.720s | 40.672us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| gpio_csr_rw | 0.750s | 81.165us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 1.240s | 77.551us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 2 | 2 | 100.00 | |||
| gpio_random_dout_din | 1.070s | 111.108us | 1 | 1 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.210s | 76.748us | 1 | 1 | 100.00 | |
| out_in_regs_read_write | 1 | 1 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 0.790s | 22.252us | 1 | 1 | 100.00 | |
| gpio_interrupt_programming | 1 | 1 | 100.00 | |||
| gpio_intr_rand_pgm | 0.970s | 291.093us | 1 | 1 | 100.00 | |
| random_interrupt_trigger | 1 | 1 | 100.00 | |||
| gpio_rand_intr_trigger | 1.730s | 106.329us | 1 | 1 | 100.00 | |
| interrupt_and_noise_filter | 1 | 1 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 2.010s | 266.671us | 1 | 1 | 100.00 | |
| noise_filter_stress | 1 | 1 | 100.00 | |||
| gpio_filter_stress | 7.470s | 783.245us | 1 | 1 | 100.00 | |
| regs_long_reads_and_writes | 1 | 1 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 3.170s | 1440.854us | 1 | 1 | 100.00 | |
| full_random | 1 | 1 | 100.00 | |||
| gpio_full_random | 1.130s | 361.636us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| gpio_stress_all | 31.530s | 8663.753us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| gpio_alert_test | 0.790s | 13.348us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| gpio_intr_test | 0.740s | 63.860us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 2.210s | 601.875us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 2.210s | 601.875us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.750s | 81.165us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 1.140s | 288.685us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 1.240s | 77.551us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.660s | 49.360us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.750s | 81.165us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 1.140s | 288.685us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 1.240s | 77.551us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.660s | 49.360us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| gpio_tl_intg_err | 1.160s | 66.142us | 1 | 1 | 100.00 | |
| gpio_sec_cm | 0.980s | 120.290us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| gpio_tl_intg_err | 1.160s | 66.142us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 0 | 1 | 0.00 | |||
| gpio_rand_straps | 0.740s | 5.224us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 1.770s | 83.799us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| gpio_inp_prd_cnt | 0.710s | 73.344us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | 1 test run | |||
| gpio_stress_all_with_rand_reset | 73424133930873342754589619693072614679137073259663968523130787018781312953689 | 78 |
UVM_INFO @ 83798880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (gpio_scoreboard.sv:248) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 1 test run | |||
| gpio_rand_straps | 95942066448377317176382657318012998805388608375979533566729830210719700695891 | 75 |
UVM_INFO @ 5224474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|