Simulation Results: hmac

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.17 %
  • code
  • 96.00 %
  • assert
  • 97.17 %
  • func
  • 29.35 %
  • block
  • 97.51 %
  • line
  • 98.44 %
  • branch
  • 93.76 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.000s 194.284us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 31.515us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 28.080us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.000s 588.709us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.000s 304.380us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 140.948us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 28.080us 1 1 100.00
hmac_csr_aliasing 4.000s 304.380us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 76.000s 9177.752us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 5.000s 307.266us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 194.000s 32918.653us 1 1 100.00
hmac_test_sha384_vectors 483.000s 83755.732us 1 1 100.00
hmac_test_sha512_vectors 23.000s 338.170us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 303.289us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 500.526us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 503.378us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 24.000s 10002.777us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 280.000s 40335.778us 1 1 100.00
error 1 1 100.00
hmac_error 48.000s 6359.422us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 6.000s 409.277us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.000s 194.284us 1 1 100.00
hmac_long_msg 76.000s 9177.752us 1 1 100.00
hmac_back_pressure 5.000s 307.266us 1 1 100.00
hmac_datapath_stress 280.000s 40335.778us 1 1 100.00
hmac_burst_wr 24.000s 10002.777us 1 1 100.00
hmac_stress_all 896.000s 30086.063us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.000s 194.284us 1 1 100.00
hmac_long_msg 76.000s 9177.752us 1 1 100.00
hmac_back_pressure 5.000s 307.266us 1 1 100.00
hmac_datapath_stress 280.000s 40335.778us 1 1 100.00
hmac_wipe_secret 6.000s 409.277us 1 1 100.00
hmac_test_sha256_vectors 194.000s 32918.653us 1 1 100.00
hmac_test_sha384_vectors 483.000s 83755.732us 1 1 100.00
hmac_test_sha512_vectors 23.000s 338.170us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 303.289us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 500.526us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 503.378us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.000s 194.284us 1 1 100.00
hmac_long_msg 76.000s 9177.752us 1 1 100.00
hmac_back_pressure 5.000s 307.266us 1 1 100.00
hmac_datapath_stress 280.000s 40335.778us 1 1 100.00
hmac_burst_wr 24.000s 10002.777us 1 1 100.00
hmac_error 48.000s 6359.422us 1 1 100.00
hmac_wipe_secret 6.000s 409.277us 1 1 100.00
hmac_test_sha256_vectors 194.000s 32918.653us 1 1 100.00
hmac_test_sha384_vectors 483.000s 83755.732us 1 1 100.00
hmac_test_sha512_vectors 23.000s 338.170us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 303.289us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 500.526us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 503.378us 1 1 100.00
hmac_stress_all 896.000s 30086.063us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 896.000s 30086.063us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 114.242us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 19.175us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 47.603us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 47.603us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 31.515us 1 1 100.00
hmac_csr_rw 2.000s 28.080us 1 1 100.00
hmac_csr_aliasing 4.000s 304.380us 1 1 100.00
hmac_same_csr_outstanding 2.000s 111.833us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 31.515us 1 1 100.00
hmac_csr_rw 2.000s 28.080us 1 1 100.00
hmac_csr_aliasing 4.000s 304.380us 1 1 100.00
hmac_same_csr_outstanding 2.000s 111.833us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 131.272us 1 1 100.00
hmac_tl_intg_err 5.000s 938.285us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 5.000s 938.285us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.000s 194.284us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.000s 23.718us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 146.000s 107067.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 112.912us 1 1 100.00