Simulation Results

Simulation Results: i2c

23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.21 %

code
86.00 %

assert
97.25 %

func
81.38 %

block
96.14 %

line
95.51 %

branch
93.09 %

toggle
72.68 %

FSM
82.73 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	234.000s	2286.851us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	11.000s	4541.524us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	77.598us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	20.332us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	7.000s	557.409us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	3.000s	407.195us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	75.809us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	20.332us	1	1	100.00
	i2c_csr_aliasing	3.000s	407.195us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	29.140us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	2362.000s	4875.330us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	32.000s	8717.305us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	32.793us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3600.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1143.000s	8781.092us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	246.318us	1	1	100.00
	i2c_host_fifo_fmt_empty	63.000s	4056.758us	1	1	100.00
	i2c_host_fifo_reset_rx	7.000s	171.871us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	886.000s	12237.519us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	32.000s	8283.027us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.000s	15.979us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.000s	1065.291us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	97.000s	26346.502us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.000s	712.026us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	25.000s	3072.441us	1	1	100.00
	i2c_target_intr_smoke	8.000s	2378.847us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	457.470us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	411.453us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	25.000s	3072.441us	1	1	100.00
	i2c_target_intr_stress_wr	1351.000s	21244.371us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	9.000s	5226.954us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	95.000s	2888.433us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.000s	4287.759us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	8.000s	10054.240us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	4.000s	1995.025us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	120.422us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	32.000s	8717.305us	1	1	100.00
	i2c_host_perf_precise	3.000s	128.557us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	32.000s	8283.027us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.000s	120.699us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	6.000s	10302.290us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	1169.555us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	695.472us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	4.000s	303.438us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	1059.559us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	26.811us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	42.076us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	34.103us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	34.103us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	77.598us	1	1	100.00
	i2c_csr_rw	1.000s	20.332us	1	1	100.00
	i2c_csr_aliasing	3.000s	407.195us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	194.826us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	77.598us	1	1	100.00
	i2c_csr_rw	1.000s	20.332us	1	1	100.00
	i2c_csr_aliasing	3.000s	407.195us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	194.826us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	860.296us	1	1	100.00
	i2c_sec_cm	1.000s	253.883us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	860.296us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	20.000s	1935.552us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	127.276us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	1.000s	35.383us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	32974232848259293533740122966794301005164049558056731004787588283946157453194	89	UVM_INFO @ 29140226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	10074467867469252356235798941932216808375815517944893397444511744045179590112	94	UVM_INFO @ 35382628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	77926105212819961130636131478034130201650551183548978104217114416452968815671	90	UVM_INFO @ 15978897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				2 test runs
	i2c_host_fifo_watermark	17235087878295918837082692516082537419836363750346918720696061992711831139190	None
	i2c_target_stress_wr	75553737922098332806807543458072550149205305646339929550111559875407519260361	None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	25241868660340601019804942350150243200424896535645527761877661986539178316436	93	UVM_INFO @ 1065290639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/i2c-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_i2c_/rtl/i2c_fifos.sv,320): Assertion TxWriteStableBeforeHandshake_A has failed (* cycles, starting * PS)				1 test run
	i2c_target_unexp_stop	110990488477945581953746775734123416415646190014189433811555153443486136291638	89	UVM_ERROR @ 127276192 ps: (i2c_fifos.sv:320) [ASSERT FAILED] TxWriteStableBeforeHandshake_A UVM_INFO @ 127276192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	18161877605159225223870598197282666279571512763578355008483481761524294312878	88	UVM_INFO @ 10054240394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	78804414999613391368686752521934646161067372956997680968952888274678719234201	98	UVM_INFO @ 1935552296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---