Simulation Results

Simulation Results: kmac/masked

23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
80.82 %

code
68.23 %

assert
97.05 %

func
77.18 %

line
95.47 %

branch
89.44 %

cond
85.14 %

toggle
29.31 %

FSM
41.77 %

Validation stages

V1		100.00%
V2		68.97%
V2S		75.00%
V3		0.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	kmac_smoke	39.020s	1582.894us	1	1	100.00
csr_hw_reset				1	1	100.00
	kmac_csr_hw_reset	0.900s	41.944us	1	1	100.00
csr_rw				1	1	100.00
	kmac_csr_rw	1.170s	57.755us	1	1	100.00
csr_bit_bash				1	1	100.00
	kmac_csr_bit_bash	12.580s	837.561us	1	1	100.00
csr_aliasing				1	1	100.00
	kmac_csr_aliasing	5.620s	277.579us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	kmac_csr_mem_rw_with_rand_reset	1.970s	81.703us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	kmac_csr_rw	1.170s	57.755us	1	1	100.00
	kmac_csr_aliasing	5.620s	277.579us	1	1	100.00
mem_walk				1	1	100.00
	kmac_mem_walk	0.870s	13.877us	1	1	100.00
mem_partial_access				1	1	100.00
	kmac_mem_partial_access	0.980s	59.435us	1	1	100.00

20/29 passed

68.97 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
long_msg_and_output				1	1	100.00
	kmac_long_msg_and_output	3058.680s	217796.082us	1	1	100.00
burst_write				1	1	100.00
	kmac_burst_write	637.290s	18882.963us	1	1	100.00
test_vectors				8	8	100.00
	kmac_test_vectors_sha3_224	31.030s	4446.824us	1	1	100.00
	kmac_test_vectors_sha3_256	1528.740s	24495.703us	1	1	100.00
	kmac_test_vectors_sha3_384	1497.130s	308892.876us	1	1	100.00
	kmac_test_vectors_sha3_512	13.930s	2428.266us	1	1	100.00
	kmac_test_vectors_shake_128	221.550s	70000.452us	1	1	100.00
	kmac_test_vectors_shake_256	2267.700s	557843.607us	1	1	100.00
	kmac_test_vectors_kmac	2.270s	80.033us	1	1	100.00
	kmac_test_vectors_kmac_xof	2.710s	1587.875us	1	1	100.00
sideload				1	1	100.00
	kmac_sideload	89.590s	9206.309us	1	1	100.00
app				0	1	0.00
	kmac_app	8.680s	2075.163us	0	1	0.00
app_with_partial_data				0	1	0.00
	kmac_app_with_partial_data	2.010s	1407.531us	0	1	0.00
entropy_refresh				0	1	0.00
	kmac_entropy_refresh	1.200s	5.285us	0	1	0.00
error				0	1	0.00
	kmac_error	16.130s	1194.870us	0	1	0.00
key_error				0	1	0.00
	kmac_key_error	0.980s	126.513us	0	1	0.00
sideload_invalid				0	1	0.00
	kmac_sideload_invalid	1.210s	13.750us	0	1	0.00
edn_timeout_error				1	1	100.00
	kmac_edn_timeout_error	1.030s	39.806us	1	1	100.00
entropy_mode_error				1	1	100.00
	kmac_entropy_mode_error	1.030s	43.498us	1	1	100.00
entropy_ready_error				0	1	0.00
	kmac_entropy_ready_error	1.320s	144.725us	0	1	0.00
lc_escalation				0	1	0.00
	kmac_lc_escalation	1.180s	18.487us	0	1	0.00
stress_all				0	1	0.00
	kmac_stress_all	77.870s	3453.269us	0	1	0.00
intr_test				1	1	100.00
	kmac_intr_test	0.950s	16.124us	1	1	100.00
alert_test				1	1	100.00
	kmac_alert_test	1.120s	17.584us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	kmac_tl_errors	3.150s	131.064us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	kmac_tl_errors	3.150s	131.064us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	kmac_csr_hw_reset	0.900s	41.944us	1	1	100.00
	kmac_csr_rw	1.170s	57.755us	1	1	100.00
	kmac_csr_aliasing	5.620s	277.579us	1	1	100.00
	kmac_same_csr_outstanding	2.250s	199.211us	1	1	100.00
tl_d_partial_access				4	4	100.00
	kmac_csr_hw_reset	0.900s	41.944us	1	1	100.00
	kmac_csr_rw	1.170s	57.755us	1	1	100.00
	kmac_csr_aliasing	5.620s	277.579us	1	1	100.00
	kmac_same_csr_outstanding	2.250s	199.211us	1	1	100.00

V2S

6/8 passed

75.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				1	1	100.00
	kmac_shadow_reg_errors	1.890s	103.052us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	kmac_shadow_reg_errors	1.890s	103.052us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	kmac_shadow_reg_errors	1.890s	103.052us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	kmac_shadow_reg_errors	1.890s	103.052us	1	1	100.00
shadow_reg_update_error_with_csr_rw				1	1	100.00
	kmac_shadow_reg_errors_with_csr_rw	2.320s	95.509us	1	1	100.00
tl_intg_err				2	2	100.00
	kmac_sec_cm	44.040s	9674.631us	1	1	100.00
	kmac_tl_intg_err	3.780s	214.413us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	kmac_tl_intg_err	3.780s	214.413us	1	1	100.00
sec_cm_lc_escalate_en_intersig_mubi				0	1	0.00
	kmac_lc_escalation	1.180s	18.487us	0	1	0.00
sec_cm_sw_key_key_masking				1	1	100.00
	kmac_smoke	39.020s	1582.894us	1	1	100.00
sec_cm_key_sideload				1	1	100.00
	kmac_sideload	89.590s	9206.309us	1	1	100.00
sec_cm_cfg_shadowed_config_shadow				1	1	100.00
	kmac_shadow_reg_errors	1.890s	103.052us	1	1	100.00
sec_cm_fsm_sparse				1	1	100.00
	kmac_sec_cm	44.040s	9674.631us	1	1	100.00
sec_cm_ctr_redun				1	1	100.00
	kmac_sec_cm	44.040s	9674.631us	1	1	100.00
sec_cm_packer_ctr_redun				1	1	100.00
	kmac_sec_cm	44.040s	9674.631us	1	1	100.00
sec_cm_cfg_shadowed_config_regwen				1	1	100.00
	kmac_smoke	39.020s	1582.894us	1	1	100.00
sec_cm_fsm_global_esc				0	1	0.00
	kmac_lc_escalation	1.180s	18.487us	0	1	0.00
sec_cm_fsm_local_esc				1	1	100.00
	kmac_sec_cm	44.040s	9674.631us	1	1	100.00
sec_cm_absorbed_ctrl_mubi				0	1	0.00
	kmac_mubi	16.250s	3453.954us	0	1	0.00
sec_cm_sw_cmd_ctrl_sparse				1	1	100.00
	kmac_smoke	39.020s	1582.894us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	kmac_stress_all_with_rand_reset	106.910s	16172.096us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [] vs []) Mismatch between unmasked_digest[] and dpi_digest[*]				7 test runs
	kmac_sideload_invalid	32398801155106837213007013792090806401928098490860477796991477563336592887743	76	UVM_INFO @ 13749940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_app	88990336887167406418983426938915915915333074542505260155329314961583101383774	81	UVM_INFO @ 2075162937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_app_with_partial_data	19001647139129548953260424690483336541652216619622523693023244774693704365629	77	UVM_INFO @ 1407530681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_entropy_refresh	22821493750480242422702248663492061192867517844837184197835798819714272823324	77	UVM_INFO @ 5285103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_error	23089594426940643141402229826747146051078184767928351500810850040633158882207	85	UVM_INFO @ 1194870021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_lc_escalation	64257201964821594808159829780812724353777231110023812766585420406260182117938	80	UVM_INFO @ 18486803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_stress_all_with_rand_reset	115061888212099168661560542097891783363579533848167765924701935026320059944727	335	UVM_INFO @ 16172096353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err)				2 test runs
	kmac_mubi	13193398670952029782511581851317336454222893383096684014265310901705868351767	83	UVM_INFO @ 3453953889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_stress_all	95201767839593844972066583138012542190044120935938209793134402572875101607339	129	UVM_INFO @ 3453269139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))'				2 test runs
	kmac_key_error	33430853616923834691357236471211332894399261387501745236114165725386635474607	78	UVM_ERROR @ 126512685 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A UVM_INFO @ 126512685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_entropy_ready_error	85279125618925527591877177754257915541461279489849857701347858608386776364000	78	UVM_ERROR @ 144725061 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A UVM_INFO @ 144725061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---