Simulation Results: lc_ctrl/volatile_unlock_disabled

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.03 %
  • code
  • 92.79 %
  • assert
  • 96.69 %
  • func
  • 86.62 %
  • block
  • 96.57 %
  • line
  • 97.26 %
  • branch
  • 91.26 %
  • toggle
  • 87.39 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 960.939us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 74.305us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.588us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 36.643us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 30.897us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 33.287us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 16.588us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 30.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 72.634us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 1116.825us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 11.827us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 268.226us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 1132.514us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 1390.585us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 1132.514us 1 1 100.00
lc_ctrl_prog_failure 2.000s 268.226us 1 1 100.00
lc_ctrl_errors 5.000s 1390.585us 1 1 100.00
lc_ctrl_security_escalation 6.000s 313.252us 1 1 100.00
lc_ctrl_jtag_state_failure 43.000s 5583.073us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 686.458us 1 1 100.00
lc_ctrl_jtag_errors 14.000s 4141.999us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.000s 85.774us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 1459.984us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 686.458us 1 1 100.00
lc_ctrl_jtag_errors 14.000s 4141.999us 1 1 100.00
lc_ctrl_jtag_access 2.000s 294.836us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.000s 1717.308us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 91.194us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 977.050us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.000s 2290.725us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.000s 1100.180us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.000s 25.557us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 367.090us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 141.131us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 15.000s 584.719us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 16.254us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 132.000s 22528.107us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 40.053us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 73.775us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 73.775us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 74.305us 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.588us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 30.897us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 55.623us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 74.305us 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.588us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 30.897us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 55.623us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 612.621us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 306.981us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 306.981us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 1116.825us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1132.514us 1 1 100.00
lc_ctrl_sec_cm 3.000s 612.621us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1132.514us 1 1 100.00
lc_ctrl_sec_cm 3.000s 612.621us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 1132.514us 1 1 100.00
lc_ctrl_sec_cm 3.000s 612.621us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 1132.514us 1 1 100.00
lc_ctrl_sec_cm 3.000s 612.621us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1132.514us 1 1 100.00
lc_ctrl_sec_cm 3.000s 612.621us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1132.514us 1 1 100.00
lc_ctrl_sec_cm 3.000s 612.621us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 1132.514us 1 1 100.00
lc_ctrl_sec_cm 3.000s 612.621us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 1132.514us 1 1 100.00
lc_ctrl_sec_cm 3.000s 612.621us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 313.252us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 72.634us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 1459.984us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.000s 4136.709us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.000s 4136.709us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.000s 848.636us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 2642.676us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 2642.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 2.000s 108.806us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 6182721856592620610527864983413987913132273442703608277858773725137327307533 160
UVM_INFO @ 108806190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---