Simulation Results: lc_ctrl/volatile_unlock_enabled

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.01 %
  • code
  • 93.12 %
  • assert
  • 95.97 %
  • func
  • 86.94 %
  • block
  • 97.07 %
  • line
  • 97.63 %
  • branch
  • 92.56 %
  • toggle
  • 87.04 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 48.265us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 31.627us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 18.270us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 135.143us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 41.786us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 54.291us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 18.270us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 41.786us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 871.986us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 1049.418us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 29.068us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 119.426us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 1728.659us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.000s 410.412us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 4.000s 1728.659us 1 1 100.00
lc_ctrl_prog_failure 3.000s 119.426us 1 1 100.00
lc_ctrl_errors 7.000s 410.412us 1 1 100.00
lc_ctrl_security_escalation 6.000s 715.644us 1 1 100.00
lc_ctrl_jtag_state_failure 2.000s 74.231us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.000s 269.566us 1 1 100.00
lc_ctrl_jtag_errors 16.000s 9616.987us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.000s 1108.414us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.000s 2496.152us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 269.566us 1 1 100.00
lc_ctrl_jtag_errors 16.000s 9616.987us 1 1 100.00
lc_ctrl_jtag_access 4.000s 352.931us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 16.000s 3329.457us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 262.092us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 207.761us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.000s 2096.364us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.000s 206.173us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 55.697us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 1141.242us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 97.380us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 14.000s 1678.653us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 25.773us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 24.000s 18049.305us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 62.235us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 98.280us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 98.280us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 31.627us 1 1 100.00
lc_ctrl_csr_rw 1.000s 18.270us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 41.786us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 245.643us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 31.627us 1 1 100.00
lc_ctrl_csr_rw 1.000s 18.270us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 41.786us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 245.643us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 262.910us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 527.438us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 527.438us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 1049.418us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1728.659us 1 1 100.00
lc_ctrl_sec_cm 3.000s 262.910us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1728.659us 1 1 100.00
lc_ctrl_sec_cm 3.000s 262.910us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 1728.659us 1 1 100.00
lc_ctrl_sec_cm 3.000s 262.910us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 1728.659us 1 1 100.00
lc_ctrl_sec_cm 3.000s 262.910us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1728.659us 1 1 100.00
lc_ctrl_sec_cm 3.000s 262.910us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1728.659us 1 1 100.00
lc_ctrl_sec_cm 3.000s 262.910us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1728.659us 1 1 100.00
lc_ctrl_sec_cm 3.000s 262.910us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 1728.659us 1 1 100.00
lc_ctrl_sec_cm 3.000s 262.910us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 715.644us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 871.986us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.000s 2496.152us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 1267.117us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 1267.117us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 479.749us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 554.484us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 554.484us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 15.000s 8611.869us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_failure 68738960077774372858023117838064444683750839139597519234149475792068297259690 177
UVM_INFO @ 74230865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---