Simulation Results: mbx

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.05 %
  • code
  • 88.11 %
  • assert
  • 96.96 %
  • func
  • 76.07 %
  • block
  • 95.74 %
  • line
  • 96.02 %
  • branch
  • 88.65 %
  • toggle
  • 79.67 %
Validation stages
V1
83.33%
V2
63.64%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 60.000s 15060.076us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 101.615us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 26.797us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 2.000s 193.990us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 28.369us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 1.392us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 26.797us 1 1 100.00
mbx_csr_aliasing 2.000s 28.369us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 4.000s 1988.814us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 7.000s 3234.817us 0 1 0.00
mbx_imbx_oob 0 1 0.00
mbx_imbx_oob 7.000s 358.822us 0 1 0.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 15.000s 1123.951us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 14.480us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 22.035us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 6.488us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 6.488us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 101.615us 1 1 100.00
mbx_csr_rw 2.000s 26.797us 1 1 100.00
mbx_csr_aliasing 2.000s 28.369us 1 1 100.00
mbx_same_csr_outstanding 2.000s 33.528us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 101.615us 1 1 100.00
mbx_csr_rw 2.000s 26.797us 1 1 100.00
mbx_csr_aliasing 2.000s 28.369us 1 1 100.00
mbx_same_csr_outstanding 2.000s 33.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 740.356us 1 1 100.00
mbx_sec_cm 2.000s 13.260us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 2 test runs
mbx_stress_zero_delays 23489089833583047533636923388479021561254199824650641996728251629445434588101 722
UVM_INFO @ 3234816960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_imbx_oob 44495789660351869218147079698010514496559471138274012906536367190670060300756 128
UVM_INFO @ 358822372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 13281627294284384075391540563320185146476092912039842258321804997805337718769 85
TL item was: req: (cip_tl_seq_item@18212) { a_addr: 'h43948ab0 a_data: 'hfb61e05d a_mask: 'h9 a_size: 'h2 a_param: 'h0 a_source: 'h6c a_opcode: 'h1 a_user: 'h25090 d_param: 'h0 d_source: 'h6c d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 6487558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 33903844025162541937926248258097768474590819768935068784911527033300636965263 86
TL item was: req: (cip_tl_seq_item@20789) { a_addr: 'hd7affef4 a_data: 'hacc4ce61 a_mask: 'h0 a_size: 'h0 a_param: 'h0 a_source: 'hf1 a_opcode: 'h1 a_user: 'h25ac2 d_param: 'h0 d_source: 'hf1 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 1392476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed 1 test run
mbx_stress 59953409865157843462895409191179824713772695244865892771039891090952797648397 282
UVM_ERROR @ 1988814232 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 1988814232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---