Simulation Results: otbn

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.38 %
  • code
  • 86.33 %
  • assert
  • 89.90 %
  • func
  • 94.92 %
  • block
  • 99.29 %
  • line
  • 99.47 %
  • branch
  • 94.81 %
  • toggle
  • 84.85 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 15.000s 55.649us 1 1 100.00
single_binary 1 1 100.00
otbn_single 7.000s 26.642us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 27.973us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 6.000s 20.131us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 9.000s 213.656us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 62.731us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 37.997us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 6.000s 20.131us 1 1 100.00
otbn_csr_aliasing 4.000s 62.731us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 136.000s 26828.912us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 24.000s 2196.797us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 28.000s 328.858us 1 1 100.00
multi_error 0 1 0.00
otbn_multi_err 36.000s 118.237us 0 1 0.00
back_to_back 1 1 100.00
otbn_multi 49.000s 919.078us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 86.000s 209.625us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 11.000s 71.622us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 26.454us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 95.791us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 26.665us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 16.473us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 1485.128us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 1485.128us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 27.973us 1 1 100.00
otbn_csr_rw 6.000s 20.131us 1 1 100.00
otbn_csr_aliasing 4.000s 62.731us 1 1 100.00
otbn_same_csr_outstanding 4.000s 15.125us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 27.973us 1 1 100.00
otbn_csr_rw 6.000s 20.131us 1 1 100.00
otbn_csr_aliasing 4.000s 62.731us 1 1 100.00
otbn_same_csr_outstanding 4.000s 15.125us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 10.000s 281.733us 1 1 100.00
otbn_dmem_err 9.000s 62.638us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 10.000s 168.934us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 202.365us 1 1 100.00
otbn_mac_bignum_acc_err 12.000s 120.746us 1 1 100.00
otbn_urnd_err 5.000s 44.614us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 10.468us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 16.000s 54.221us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 7.000s 26.147us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 335.000s 10384.290us 1 1 100.00
otbn_tl_intg_err 11.000s 134.854us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 30.000s 112.114us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 335.000s 10384.290us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 335.000s 10384.290us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 15.000s 55.649us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 9.000s 62.638us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 10.000s 281.733us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 11.000s 134.854us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 11.000s 71.622us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 281.733us 1 1 100.00
otbn_dmem_err 9.000s 62.638us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 26.454us 1 1 100.00
otbn_illegal_mem_acc 6.000s 10.468us 1 1 100.00
otbn_sec_cm 335.000s 10384.290us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 335.000s 10384.290us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 7.000s 26.642us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 281.733us 1 1 100.00
otbn_dmem_err 9.000s 62.638us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 26.454us 1 1 100.00
otbn_illegal_mem_acc 6.000s 10.468us 1 1 100.00
otbn_sec_cm 335.000s 10384.290us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 335.000s 10384.290us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 11.000s 71.622us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 281.733us 1 1 100.00
otbn_dmem_err 9.000s 62.638us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 26.454us 1 1 100.00
otbn_illegal_mem_acc 6.000s 10.468us 1 1 100.00
otbn_sec_cm 335.000s 10384.290us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 335.000s 10384.290us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 7.000s 26.642us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 7.000s 54.922us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 55.648us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 84.000s 221.528us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 84.000s 221.528us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 73.328us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 335.000s 10384.290us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 335.000s 10384.290us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 52.946us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 335.000s 10384.290us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 335.000s 10384.290us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 33.471us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 33.471us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 10.000s 24.486us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 26.642us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 26.642us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 7.000s 26.642us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 49.000s 919.078us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 7.000s 26.642us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 7.000s 26.642us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 8.000s 37.283us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 7.000s 26.642us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 335.000s 10384.290us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 144.000s 2080.152us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 80.802us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi_err 82058875619532452237408103355509182163219173936504323099087412946521713062698 332
UVM_INFO @ 118237465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 103333446273021880765106618342314374217400861711405890837979883155064516652487 146
UVM_INFO @ 112113636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---