Simulation Results: rom_ctrl/64kb

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.56 %
  • code
  • 92.01 %
  • assert
  • 96.80 %
  • func
  • 97.88 %
  • block
  • 95.34 %
  • line
  • 95.37 %
  • branch
  • 93.28 %
  • toggle
  • 84.14 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.000s 738.346us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.000s 212.758us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.000s 925.749us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.000s 216.658us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 378.887us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.000s 1666.372us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.000s 925.749us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 378.887us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.000s 1408.712us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 789.597us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 6.000s 165.811us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 12.000s 4794.739us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 8.000s 1702.498us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.000s 1162.232us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.000s 699.471us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.000s 699.471us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 212.758us 1 1 100.00
rom_ctrl_csr_rw 5.000s 925.749us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 378.887us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 219.984us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 212.758us 1 1 100.00
rom_ctrl_csr_rw 5.000s 925.749us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 378.887us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 219.984us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.000s 6502.209us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.000s 740.217us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 104.000s 1264.352us 1 1 100.00
rom_ctrl_tl_intg_err 45.000s 1310.784us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 104.000s 1264.352us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 104.000s 1264.352us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.000s 6502.209us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.000s 6502.209us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.000s 6502.209us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.000s 6502.209us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.000s 6502.209us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 104.000s 1264.352us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 104.000s 1264.352us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.000s 738.346us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.000s 738.346us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.000s 738.346us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 45.000s 1310.784us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.000s 6502.209us 1 1 100.00
rom_ctrl_kmac_err_chk 8.000s 1702.498us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.000s 6502.209us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.000s 6502.209us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.000s 6502.209us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.000s 740.217us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 104.000s 1264.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 103.000s 6400.392us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 87266165953579143086257191504921833803687437680668030762965715850820013900531 88
UVM_INFO @ 165811280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---