Simulation Results

Simulation Results: rv_dm/use_dmi_interface

23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.12 %

code
74.34 %

assert
95.50 %

func
91.52 %

block
90.19 %

line
90.14 %

branch
73.39 %

toggle
71.35 %

FSM
62.50 %

Validation stages

V1		96.30%
V2		73.91%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	31.000s	841.729us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	32.000s	559.107us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	30.000s	373.917us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	37.000s	11423.452us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	32.000s	155.131us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	40.000s	7385.104us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	35.000s	1745.536us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	31.000s	1707.749us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	43.000s	47441.988us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	30.000s	381.568us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	30.000s	176.287us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	32.000s	173.824us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	30.000s	335.165us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	32.000s	637.759us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	32.000s	987.312us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	30.000s	584.667us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	32.000s	399.743us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	30.000s	381.568us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	32.000s	402.040us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	32.000s	949.753us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	32.000s	173.824us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	31.000s	96.730us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	30.000s	297.076us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	31.000s	149.824us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	48.000s	2412.740us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	57.000s	2140.179us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	31.000s	132.417us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	57.000s	2140.179us	1	1	100.00
	rv_dm_csr_rw	31.000s	149.824us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	32.000s	68.029us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	30.000s	38.029us	1	1	100.00

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	31.000s	841.729us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	32.000s	662.916us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	31.000s	358.209us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	30.000s	339.162us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	32.000s	2222.167us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	46.000s	10386.837us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	30.000s	73.451us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	43.000s	12852.497us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	29.000s	93.241us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	31.000s	110.598us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	31.000s	2539.016us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	30.000s	263.441us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	30.000s	92.321us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	32.000s	11941.603us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	72.000s	9314.419us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	30.000s	146.766us	1	1	100.00
stress_all				1	1	100.00
	rv_dm_stress_all	41.000s	7745.720us	1	1	100.00
alert_test				1	1	100.00
	rv_dm_alert_test	30.000s	138.171us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	32.000s	259.625us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	32.000s	259.625us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	57.000s	2140.179us	1	1	100.00
	rv_dm_csr_hw_reset	30.000s	297.076us	1	1	100.00
	rv_dm_csr_rw	31.000s	149.824us	1	1	100.00
	rv_dm_same_csr_outstanding	33.000s	1496.176us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	57.000s	2140.179us	1	1	100.00
	rv_dm_csr_hw_reset	30.000s	297.076us	1	1	100.00
	rv_dm_csr_rw	31.000s	149.824us	1	1	100.00
	rv_dm_same_csr_outstanding	33.000s	1496.176us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	31.000s	446.815us	1	1	100.00
	rv_dm_tl_intg_err	36.000s	4130.702us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	36.000s	4130.702us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	31.000s	2539.016us	1	1	100.00
	rv_dm_debug_disabled	31.000s	81.543us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	31.000s	2539.016us	1	1	100.00
	rv_dm_debug_disabled	31.000s	81.543us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	31.000s	841.729us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	30.000s	252.368us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	109.523us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	109.523us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	30.000s	252.368us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	34.000s	104.024us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	448.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	20730260928345518655126536643012692990326253239145837610640081628384370590053	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_bad_sba_tl_access	101467334104286607175676927555875571584511594165814265559347496787717228024958	135	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23975
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	34055527065812853954477973752865988827219034367049492650894262364815892139875	107	UVM_INFO @ 73450727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	53100622801441751128113797265446773363808191275623994695231012348853786937484	107	UVM_INFO @ 93241130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				2 test runs
	rv_dm_mem_tl_access_resuming	47420377708633938226851715721315038761101127826410117537342531850761538797795	87	UVM_INFO @ 335164888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	102948499498195565863044631861532261941185936738809332296725529544497230997852	91	UVM_INFO @ 104023639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	49465551865288329365816643514421024668753236672221126411763467057173957719604	87	UVM_INFO @ 92320745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	70229285393159220202454881312517720287662078733127501352547218253983406470718	87	UVM_INFO @ 110598152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	24785378371943896878176664765682688187085588274789685380364727552122666926836	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---