Simulation Results: rv_timer

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 98.09 %
  • code
  • 95.85 %
  • assert
  • 98.42 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 3.000s 892.061us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 15.464us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 20.693us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 556.287us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 54.073us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 375.429us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 20.693us 1 1 100.00
rv_timer_csr_aliasing 1.000s 54.073us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.000s 60.806us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.000s 286.470us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 83.000s 171307.785us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 83.000s 171307.785us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.000s 5005.595us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 44.973us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 47.031us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 87.864us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 87.864us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 15.464us 1 1 100.00
rv_timer_csr_rw 1.000s 20.693us 1 1 100.00
rv_timer_csr_aliasing 1.000s 54.073us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 31.869us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 15.464us 1 1 100.00
rv_timer_csr_rw 1.000s 20.693us 1 1 100.00
rv_timer_csr_aliasing 1.000s 54.073us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 31.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 2.000s 80.170us 1 1 100.00
rv_timer_tl_intg_err 2.000s 827.485us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 827.485us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 651.885us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 185.369us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 35.000s 23464.040us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 78191031874838564977794675742806511916752699082860494999133606903035213247390 84
UVM_INFO @ 651884529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 37618155025172402439175797438302093025428404940083898727276949993286227921251 84
UVM_INFO @ 60806097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:347) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 105777355816939112139171107923022376286954451507626713743826204873263843659872 84
UVM_INFO @ 185368929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---