Simulation Results: spi_device/1r1w

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.63 %
  • code
  • 89.48 %
  • assert
  • 95.40 %
  • func
  • 69.01 %
  • block
  • 98.33 %
  • line
  • 98.76 %
  • branch
  • 96.96 %
  • toggle
  • 72.61 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 262.000s 26292.129us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 26.948us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.000s 40.872us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 25.000s 4081.314us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 7.000s 340.505us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 4.000s 305.676us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.000s 40.872us 1 1 100.00
spi_device_csr_aliasing 7.000s 340.505us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 20.236us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 139.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.000s 22.183us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 1.248us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 4.176us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 11.525us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 11.525us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 15.000s 6561.001us 1 1 100.00
spi_device_tpm_sts_read 2.000s 103.659us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 10.000s 2059.512us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 12.000s 2963.729us 1 1 100.00
spi_device_flash_all 35.000s 4053.339us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 8.000s 444.509us 1 1 100.00
spi_device_flash_all 35.000s 4053.339us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 8.000s 444.509us 1 1 100.00
spi_device_flash_all 35.000s 4053.339us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 35.000s 4053.339us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 14.000s 3002.393us 1 1 100.00
spi_device_flash_all 35.000s 4053.339us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 14.000s 3002.393us 1 1 100.00
spi_device_flash_all 35.000s 4053.339us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 14.000s 3002.393us 1 1 100.00
spi_device_flash_all 35.000s 4053.339us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 14.000s 3002.393us 1 1 100.00
spi_device_flash_all 35.000s 4053.339us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 14.000s 3002.393us 1 1 100.00
spi_device_flash_all 35.000s 4053.339us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.000s 305.571us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 35.000s 15794.445us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 35.000s 15794.445us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 35.000s 15794.445us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 21.000s 1016.916us 1 1 100.00
spi_device_read_buffer_direct 5.000s 226.246us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 35.000s 15794.445us 1 1 100.00
spi_device_flash_all 35.000s 4053.339us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 35.000s 4053.339us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 35.000s 4053.339us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 5.000s 942.183us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 5.000s 942.183us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 169.000s 16635.110us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 262.000s 26292.129us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 401.000s 163098.888us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 2.000s 289.791us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 12.694us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 13.805us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 403.633us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 403.633us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 26.948us 1 1 100.00
spi_device_csr_rw 2.000s 40.872us 1 1 100.00
spi_device_csr_aliasing 7.000s 340.505us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 45.982us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 26.948us 1 1 100.00
spi_device_csr_rw 2.000s 40.872us 1 1 100.00
spi_device_csr_aliasing 7.000s 340.505us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 45.982us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 141.868us 1 1 100.00
spi_device_tl_intg_err 14.000s 2586.458us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 14.000s 2586.458us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 53629678761219477493254784181660875253076259473983436828198738980203631430264 87
UVM_ERROR @ 967230 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[980] not found within the scope .
UVM_ERROR @ 967230 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[980] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 29035790922200558812108251856605219107781915618637809786284975061361485620182 85
UVM_ERROR @ 1508677 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2de [1011011110] vs 0x0 [0])
UVM_ERROR @ 1579677 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x23e [1000111110] vs 0x0 [0])
UVM_ERROR @ 1612677 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x354 [1101010100] vs 0x0 [0])
UVM_ERROR @ 1639677 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x19e [110011110] vs 0x0 [0])