Simulation Results: sram_ctrl/main

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.92 %
  • code
  • 95.46 %
  • assert
  • 98.10 %
  • func
  • 94.20 %
  • block
  • 95.77 %
  • line
  • 96.46 %
  • branch
  • 93.53 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 7.000s 3069.688us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 20.467us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.448us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 126.619us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 24.292us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 2075.224us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 14.448us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 24.292us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 110.000s 13430.549us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 91.000s 4667.960us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 11.000s 11652.811us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 142.000s 9184.743us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 158.000s 31564.179us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 49.000s 54258.632us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 26.000s 27187.914us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 13.000s 11474.933us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 3198.331us 1 1 100.00
sram_ctrl_partial_access_b2b 301.000s 106309.638us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 3.000s 668.185us 0 1 0.00
sram_ctrl_throughput_w_partial_write 3.000s 675.828us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 3907.595us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 2775.394us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 358.080us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 238.000s 43025.533us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 15.002us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 315.976us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 315.976us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 20.467us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.448us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 24.292us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 32.302us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 20.467us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.448us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 24.292us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 32.302us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 6338.222us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 745.599us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 426.216us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 745.599us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 426.216us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 2775.394us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 2775.394us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.448us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 13.000s 11474.933us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 11474.933us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 11474.933us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 26.000s 27187.914us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 674.896us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 6338.222us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 697.980us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 3069.688us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 3069.688us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 13.000s 11474.933us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 745.599us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 26.000s 27187.914us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 745.599us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 745.599us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 7.000s 3069.688us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 745.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 32.000s 2956.016us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 91957665692005599111982972905520355749597372587390263748722671747361124092285 86
UVM_INFO @ 668185136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 18358527195119581140867709890083761970797406590212091042248079397879212364182 86
UVM_INFO @ 675828488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 80227996326298295939351928723678471627302043227782085066150606045708460703976 86
UVM_INFO @ 3907595109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---