Simulation Results: uart

 
23/07/2026 19:40:32 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.71 %
  • code
  • 73.60 %
  • assert
  • 98.85 %
  • func
  • 90.69 %
  • block
  • 98.58 %
  • line
  • 99.24 %
  • branch
  • 97.24 %
  • toggle
  • 72.91 %
  • FSM
  • 25.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 12.000s 6248.045us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 53.636us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 14.576us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 51.959us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 40.428us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 265.214us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 14.576us 1 1 100.00
uart_csr_aliasing 1.000s 40.428us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 18.000s 17030.595us 1 1 100.00
parity 2 2 100.00
uart_smoke 12.000s 6248.045us 1 1 100.00
uart_tx_rx 18.000s 17030.595us 1 1 100.00
parity_error 2 2 100.00
uart_intr 56.000s 47268.360us 1 1 100.00
uart_rx_parity_err 110.000s 196539.198us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 18.000s 17030.595us 1 1 100.00
uart_intr 56.000s 47268.360us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 43.000s 39311.873us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 63.000s 58478.069us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 46.000s 36598.131us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 56.000s 47268.360us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 56.000s 47268.360us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 56.000s 47268.360us 1 1 100.00
perf 1 1 100.00
uart_perf 164.000s 8114.039us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.000s 1612.273us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.000s 1612.273us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 13.000s 13911.888us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 5.000s 2800.268us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 6.000s 1016.776us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 6.000s 2463.930us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 234.000s 124341.187us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 264.000s 251160.933us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 1.000s 13.296us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 22.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 78.910us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 78.910us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 53.636us 1 1 100.00
uart_csr_rw 1.000s 14.576us 1 1 100.00
uart_csr_aliasing 1.000s 40.428us 1 1 100.00
uart_same_csr_outstanding 1.000s 36.145us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 53.636us 1 1 100.00
uart_csr_rw 1.000s 14.576us 1 1 100.00
uart_csr_aliasing 1.000s 40.428us 1 1 100.00
uart_same_csr_outstanding 1.000s 36.145us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 41.097us 1 1 100.00
uart_tl_intg_err 1.000s 52.485us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 52.485us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 38.000s 9048.257us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 51388082363317916298420659227991598194329634476636005897013058977463498081753 86
UVM_ERROR @ 12161065441 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 12161085849 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (83 [0x53] vs 111 [0x6f]) reg name: uart_reg_block.rdata
UVM_ERROR @ 12433695913 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 12433736729 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_stress_all 79185936524056680882752399355523462070432957657706691251775519459289818594628 177
UVM_ERROR @ 250903612238 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 250910779134 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 250921050296 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 250921050296 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0