Simulation Results: ac_range_check

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.86 %
  • code
  • 93.03 %
  • assert
  • 97.75 %
  • func
  • 57.79 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 18.000s 941.279us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 29.000s 3030.298us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 19.669us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 23.208us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 30.000s 11004.353us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 20.000s 5564.185us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 169.137us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 23.208us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 5564.185us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 61.459us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 28.000s 6501.055us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 75.000s 1799.010us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 21.573us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 18.666us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 786.203us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 786.203us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 19.669us 1 1 100.00
ac_range_check_csr_rw 2.000s 23.208us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 5564.185us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 874.733us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 19.669us 1 1 100.00
ac_range_check_csr_rw 2.000s 23.208us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 5564.185us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 874.733us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 406.120us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 406.120us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 406.120us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 406.120us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 78.000s 4748.911us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 40.120us 1 1 100.00
ac_range_check_tl_intg_err 8.000s 753.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 230.000s 14033.707us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 23.000s 1332.062us 1 1 100.00