Simulation Results: aes/gcm_unmasked

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.36 %
  • code
  • 90.37 %
  • assert
  • 97.75 %
  • func
  • 64.97 %
  • block
  • 90.40 %
  • line
  • 92.40 %
  • branch
  • 82.45 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 56.027us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 105.303us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 73.577us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 55.358us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 1790.887us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 4.000s 761.287us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 118.242us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 55.358us 1 1 100.00
aes_csr_aliasing 4.000s 761.287us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 105.303us 1 1 100.00
aes_config_error 2.000s 206.575us 1 1 100.00
aes_stress 2.000s 65.282us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 105.303us 1 1 100.00
aes_config_error 2.000s 206.575us 1 1 100.00
aes_stress 2.000s 65.282us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 65.282us 1 1 100.00
aes_b2b 5.000s 242.087us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 65.282us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 105.303us 1 1 100.00
aes_config_error 2.000s 206.575us 1 1 100.00
aes_stress 2.000s 65.282us 1 1 100.00
aes_alert_reset 3.000s 219.564us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 92.977us 1 1 100.00
aes_config_error 2.000s 206.575us 1 1 100.00
aes_alert_reset 3.000s 219.564us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 135.057us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 618.640us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 219.564us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 65.282us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 65.282us 1 1 100.00
aes_sideload 3.000s 262.885us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 81.268us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 4.000s 228.556us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 91.370us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 82.654us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 82.654us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 73.577us 1 1 100.00
aes_csr_rw 2.000s 55.358us 1 1 100.00
aes_csr_aliasing 4.000s 761.287us 1 1 100.00
aes_same_csr_outstanding 2.000s 96.334us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 73.577us 1 1 100.00
aes_csr_rw 2.000s 55.358us 1 1 100.00
aes_csr_aliasing 4.000s 761.287us 1 1 100.00
aes_same_csr_outstanding 2.000s 96.334us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 43.267us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 2.000s 133.779us 0 1 0.00
aes_control_fi 2.000s 66.805us 1 1 100.00
aes_cipher_fi 2.000s 46.309us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 81.128us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 81.128us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 81.128us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 81.128us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 130.251us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 850.653us 1 1 100.00
aes_tl_intg_err 2.000s 120.093us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 120.093us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 219.564us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 81.128us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 81.128us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 105.303us 1 1 100.00
aes_stress 2.000s 65.282us 1 1 100.00
aes_alert_reset 3.000s 219.564us 1 1 100.00
aes_core_fi 2.000s 87.980us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 206.575us 1 1 100.00
aes_stress 2.000s 65.282us 1 1 100.00
aes_core_fi 2.000s 87.980us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 81.128us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 81.719us 1 1 100.00
aes_stress 2.000s 65.282us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 65.282us 1 1 100.00
aes_sideload 3.000s 262.885us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 81.719us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 81.719us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 81.719us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 81.719us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 81.719us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 65.282us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 65.282us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 133.779us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 133.779us 0 1 0.00
aes_control_fi 2.000s 66.805us 1 1 100.00
aes_cipher_fi 2.000s 46.309us 1 1 100.00
aes_ctr_fi 2.000s 62.360us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 133.779us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 133.779us 0 1 0.00
aes_control_fi 2.000s 66.805us 1 1 100.00
aes_cipher_fi 2.000s 46.309us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 46.309us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 133.779us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 133.779us 0 1 0.00
aes_control_fi 2.000s 66.805us 1 1 100.00
aes_ctr_fi 2.000s 62.360us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 133.779us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 133.779us 0 1 0.00
aes_control_fi 2.000s 66.805us 1 1 100.00
aes_cipher_fi 2.000s 46.309us 1 1 100.00
aes_ctr_fi 2.000s 62.360us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 219.564us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 133.779us 0 1 0.00
aes_control_fi 2.000s 66.805us 1 1 100.00
aes_cipher_fi 2.000s 46.309us 1 1 100.00
aes_ctr_fi 2.000s 62.360us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 133.779us 0 1 0.00
aes_control_fi 2.000s 66.805us 1 1 100.00
aes_cipher_fi 2.000s 46.309us 1 1 100.00
aes_ctr_fi 2.000s 62.360us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 133.779us 0 1 0.00
aes_control_fi 2.000s 66.805us 1 1 100.00
aes_ctr_fi 2.000s 62.360us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 133.779us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 133.779us 0 1 0.00
aes_control_fi 2.000s 66.805us 1 1 100.00
aes_cipher_fi 2.000s 46.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 18.053us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 32856234134385646379991073527935675521684444805522075124564958632221474134409 2078
UVM_INFO @ 43266670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 25701386441983559005745407499792610446850310706773283727329973404749518801411 9777
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 1 test run
aes_stress_all 5563346669731382977376988010307058786513340911526231052733338018698362102228 12320
TEST FAILED MESSAGES DID NOT MATCH
0 d2 40 40 0
1 00 b4 b4 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 48049280230856172345203076051647511258947087244071089047116799540817544782130 140
UVM_INFO @ 18052805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---