Simulation Results: alert_handler

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.65 %
  • code
  • 90.49 %
  • assert
  • 98.56 %
  • func
  • 73.89 %
  • line
  • 99.74 %
  • branch
  • 98.43 %
  • cond
  • 91.88 %
  • toggle
  • 84.99 %
  • FSM
  • 77.42 %
Validation stages
V1
100.00%
V2
89.47%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 64.380s 1686.796us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.590s 53.353us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 2.790s 83.480us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 246.500s 6093.444us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 45.660s 2457.917us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.250s 125.616us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 2.790s 83.480us 1 1 100.00
alert_handler_csr_aliasing 45.660s 2457.917us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 251.410s 13137.402us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 23.700s 695.289us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1609.800s 81862.505us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 23.140s 509.558us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 64.380s 1686.796us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 3.280s 141.199us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 59.880s 3290.539us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 249.730s 60343.307us 1 1 100.00
lpg 1 2 50.00
alert_handler_lpg 873.680s 87695.201us 0 1 0.00
alert_handler_lpg_stub_clk 1363.130s 22499.821us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2552.840s 65180.153us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 4.630s 189.236us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.300s 118.532us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.270s 12.659us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 12.590s 952.542us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 12.590s 952.542us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.590s 53.353us 1 1 100.00
alert_handler_csr_rw 2.790s 83.480us 1 1 100.00
alert_handler_csr_aliasing 45.660s 2457.917us 1 1 100.00
alert_handler_same_csr_outstanding 8.850s 99.291us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.590s 53.353us 1 1 100.00
alert_handler_csr_rw 2.790s 83.480us 1 1 100.00
alert_handler_csr_aliasing 45.660s 2457.917us 1 1 100.00
alert_handler_same_csr_outstanding 8.850s 99.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 228.630s 9307.236us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 228.630s 9307.236us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 228.630s 9307.236us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 228.630s 9307.236us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 456.650s 6804.619us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 15.460s 1590.344us 1 1 100.00
alert_handler_tl_intg_err 2.430s 42.148us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.430s 42.148us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 228.630s 9307.236us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 64.380s 1686.796us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 64.380s 1686.796us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 64.380s 1686.796us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 64.380s 1686.796us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 23.140s 509.558us 1 1 100.00
sec_cm_lpg_intersig_mubi 0 1 0.00
alert_handler_lpg 873.680s 87695.201us 0 1 0.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 23.140s 509.558us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1609.800s 81862.505us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1609.800s 81862.505us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.460s 1590.344us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.460s 1590.344us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.460s 1590.344us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.460s 1590.344us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 15.460s 1590.344us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.460s 1590.344us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.460s 1590.344us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.460s 1590.344us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 15.460s 1590.344us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 5.430s 215.082us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalAlertPingFail) 1 test run
alert_handler_lpg 6083676970112432301770033416196407651908278155887438010114695464789563544687 81
UVM_INFO @ 87695201391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 38401474230279952331564589287642193727458288740951971393017142916393441068390 132
UVM_INFO @ 189236051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 36953655616675103926791780389567493349282072784367417503257441758294523195621 83
UVM_INFO @ 215081660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---