Simulation Results: clkmgr

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.79 %
  • code
  • 67.77 %
  • assert
  • 88.02 %
  • func
  • 65.58 %
  • line
  • 81.36 %
  • branch
  • 86.53 %
  • cond
  • 75.32 %
  • toggle
  • 95.66 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
53.85%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.170s 27.880us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.850s 19.629us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.860s 4.270us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.350s 82.670us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.710s 3.786us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.920s 6.637us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.860s 4.270us 0 1 0.00
clkmgr_csr_aliasing 0.710s 3.786us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.920s 20.194us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.980s 33.030us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.870s 37.667us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.170s 27.880us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.740s 8.674us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.630s 1.496us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.740s 8.674us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 3.440s 349.979us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.480s 49.790us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.950s 59.755us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.950s 59.755us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 0.850s 19.629us 1 1 100.00
clkmgr_csr_rw 0.860s 4.270us 0 1 0.00
clkmgr_csr_aliasing 0.710s 3.786us 0 1 0.00
clkmgr_same_csr_outstanding 0.980s 12.906us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 0.850s 19.629us 1 1 100.00
clkmgr_csr_rw 0.860s 4.270us 0 1 0.00
clkmgr_csr_aliasing 0.710s 3.786us 0 1 0.00
clkmgr_same_csr_outstanding 0.980s 12.906us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 89.520s 10007.734us 0 1 0.00
clkmgr_tl_intg_err 0.750s 6.196us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.140s 45.924us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.140s 45.924us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.140s 45.924us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.140s 45.924us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.720s 8.530us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.750s 6.196us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.740s 8.674us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.630s 1.496us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.140s 45.924us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.190s 61.154us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.860s 4.270us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 89.520s 10007.734us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.860s 4.270us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.860s 4.270us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 89.520s 10007.734us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.670s 4.108us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.750s 9.960us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 88927537847779902687964382880750004693692238589355655624233167249171960127464 75
UVM_INFO @ 8529800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 63955898066775343804534575983982962473278378652534002340941118264594319723356 78
UVM_INFO @ 6195517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 48563537559791011151486204788873556490134442909847321863202032642057261361283 75
UVM_INFO @ 3786217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 52540501212736580612805082865264994609900034255578097010968372803612723913420 75
UVM_INFO @ 8674086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 73340466489972443321132810713432141892604451450917719500825209819432696300910 103
UVM_INFO @ 349979123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 7487344558252834645745008206451823258880872555598814646111251852770415115024 77
UVM_INFO @ 1496445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 98417227855432689257647056140192578072717435810214026728233896757544928927671 79
UVM_INFO @ 9959871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 2 test runs
clkmgr_csr_rw 112913214139001869143197198082916334842230143368925504549423629569754812895844 76
UVM_INFO @ 4270008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 25449094713151483148212583029720307587575420813205466353867077680508083153532 76
UVM_INFO @ 6637194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 106282561064049618817859443548340519752751142451023589860843982722103507168848 74
UVM_INFO @ 4108132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 105100063704032735383631700747678120829244845269372136104302922724141255096753 83
UVM_INFO @ 10007733984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 1332105162058401230976393911600963676615543079809126521231672310459188607128 75
UVM_INFO @ 82670041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 75704972949322169992890750815438751728312564858804519164126212139930630332335 75
UVM_INFO @ 12905894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---