Simulation Results: dma

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.02 %
  • code
  • 90.03 %
  • assert
  • 96.50 %
  • func
  • 59.53 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 90.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 364.182us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 1080.808us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 6.000s 319.870us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 16.229us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 62.139us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 13.000s 1841.136us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 7.000s 568.847us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 54.899us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 62.139us 1 1 100.00
dma_csr_aliasing 7.000s 568.847us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 78.000s 13241.077us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 236.000s 97528.374us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 193.000s 71710.764us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 193.000s 71710.764us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 236.000s 97528.374us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 187.000s 79426.046us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 193.000s 71710.764us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 9.000s 793.075us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 49.000s 5002.228us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 30.747us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 44.831us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 90.209us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 90.209us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 16.229us 1 1 100.00
dma_csr_rw 1.000s 62.139us 1 1 100.00
dma_csr_aliasing 7.000s 568.847us 1 1 100.00
dma_same_csr_outstanding 2.000s 65.704us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 16.229us 1 1 100.00
dma_csr_rw 1.000s 62.139us 1 1 100.00
dma_csr_aliasing 7.000s 568.847us 1 1 100.00
dma_same_csr_outstanding 2.000s 65.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 14.000s 95.836us 1 1 100.00
dma_generic_stress 187.000s 79426.046us 1 1 100.00
dma_handshake_stress 193.000s 71710.764us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 5.000s 289.576us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 823.492us 1 1 100.00
dma_sec_cm 1.000s 18.907us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 107.000s 57410.840us 1 1 100.00
dma_longer_transfer 12.000s 1172.273us 1 1 100.00
dma_stress_all_with_rand_reset 8.000s 628.014us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 97548886865822833536255453814038399662661869154630084999723243356560775727925 131
UVM_INFO @ 628014402ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---