Simulation Results: edn/edn0

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.96 %
  • code
  • 84.47 %
  • assert
  • 94.03 %
  • func
  • 49.37 %
  • block
  • 93.95 %
  • line
  • 96.83 %
  • branch
  • 86.94 %
  • toggle
  • 73.50 %
  • FSM
  • 80.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 57.445us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 16.589us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 30.123us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.000s 71.426us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 54.926us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 24.935us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 30.123us 1 1 100.00
edn_csr_aliasing 2.000s 54.926us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 43.756us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 43.756us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 43.756us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 45.182us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 86.354us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 28.833us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 23.296us 1 1 100.00
edn_disable_auto_req_mode 2.000s 271.504us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 6.000s 845.365us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 20.829us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 38.447us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 4.000s 128.036us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 4.000s 128.036us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 16.589us 1 1 100.00
edn_csr_rw 2.000s 30.123us 1 1 100.00
edn_csr_aliasing 2.000s 54.926us 1 1 100.00
edn_same_csr_outstanding 1.000s 127.017us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 16.589us 1 1 100.00
edn_csr_rw 2.000s 30.123us 1 1 100.00
edn_csr_aliasing 2.000s 54.926us 1 1 100.00
edn_same_csr_outstanding 1.000s 127.017us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.000s 2302.183us 1 1 100.00
edn_tl_intg_err 3.000s 849.468us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 55.588us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 86.354us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 2302.183us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 2302.183us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 2302.183us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 2302.183us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 86.354us 1 1 100.00
edn_sec_cm 7.000s 2302.183us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 86.354us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 849.468us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 29.000s 1427.344us 1 1 100.00