Simulation Results: edn/edn1

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.19 %
  • code
  • 84.98 %
  • assert
  • 98.70 %
  • func
  • 80.88 %
  • line
  • 98.25 %
  • branch
  • 93.72 %
  • cond
  • 90.46 %
  • toggle
  • 94.74 %
  • FSM
  • 47.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.810s 41.933us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.820s 28.133us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.720s 140.350us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.640s 804.516us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.010s 50.941us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.720s 78.144us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.720s 140.350us 1 1 100.00
edn_csr_aliasing 1.010s 50.941us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.280s 95.423us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.280s 95.423us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.280s 95.423us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.800s 36.606us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.070s 50.555us 1 1 100.00
errs 1 1 100.00
edn_err 1.240s 154.821us 1 1 100.00
disable 2 2 100.00
edn_disable 0.760s 14.135us 1 1 100.00
edn_disable_auto_req_mode 1.000s 34.692us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.990s 514.857us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.750s 14.733us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.790s 44.343us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.680s 36.901us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.680s 36.901us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.820s 28.133us 1 1 100.00
edn_csr_rw 0.720s 140.350us 1 1 100.00
edn_csr_aliasing 1.010s 50.941us 1 1 100.00
edn_same_csr_outstanding 1.090s 308.300us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.820s 28.133us 1 1 100.00
edn_csr_rw 0.720s 140.350us 1 1 100.00
edn_csr_aliasing 1.010s 50.941us 1 1 100.00
edn_same_csr_outstanding 1.090s 308.300us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 1.980s 573.037us 1 1 100.00
edn_tl_intg_err 1.760s 208.049us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.800s 196.444us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.070s 50.555us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 1.980s 573.037us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 1.980s 573.037us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 1.980s 573.037us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 1.980s 573.037us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.070s 50.555us 1 1 100.00
edn_sec_cm 1.980s 573.037us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.070s 50.555us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.760s 208.049us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 40.750s 5585.687us 1 1 100.00