Simulation Results: entropy_src/rng_16bits

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 67.91 %
  • code
  • 81.78 %
  • assert
  • 74.34 %
  • func
  • 47.62 %
  • block
  • 94.13 %
  • line
  • 97.77 %
  • branch
  • 86.15 %
  • toggle
  • 52.58 %
  • FSM
  • 90.62 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 27.957us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 137.069us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 100.590us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 7.000s 230.114us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 37.623us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 20.795us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 100.590us 1 1 100.00
entropy_src_csr_aliasing 2.000s 37.623us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 27.957us 1 1 100.00
entropy_src_rng 167.000s 13148.113us 1 1 100.00
entropy_src_fw_ov 23.000s 13241.316us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 23.000s 13241.316us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 167.000s 13148.113us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 462.000s 13079.707us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 167.000s 13148.113us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 167.000s 13148.113us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 167.000s 13148.113us 1 1 100.00
entropy_src_intr 14.000s 1041.018us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 167.000s 13148.113us 1 1 100.00
entropy_src_functional_alerts 6.000s 187.916us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 20.000s 16995.239us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 108.720us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 36.000s 2125.293us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 22.938us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 43.896us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 127.727us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 127.727us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 137.069us 1 1 100.00
entropy_src_csr_rw 2.000s 100.590us 1 1 100.00
entropy_src_csr_aliasing 2.000s 37.623us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 108.870us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 137.069us 1 1 100.00
entropy_src_csr_rw 2.000s 100.590us 1 1 100.00
entropy_src_csr_aliasing 2.000s 37.623us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 108.870us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 411.567us 1 1 100.00
entropy_src_tl_intg_err 3.000s 187.559us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 167.000s 13148.113us 1 1 100.00
entropy_src_cfg_regwen 2.000s 32.452us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 167.000s 13148.113us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 167.000s 13148.113us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 167.000s 13148.113us 1 1 100.00
entropy_src_fw_ov 23.000s 13241.316us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 108.720us 1 1 100.00
entropy_src_sec_cm 2.000s 411.567us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 108.720us 1 1 100.00
entropy_src_sec_cm 2.000s 411.567us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 167.000s 13148.113us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 108.720us 1 1 100.00
entropy_src_sec_cm 2.000s 411.567us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 108.720us 1 1 100.00
entropy_src_sec_cm 2.000s 411.567us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 108.720us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 6.000s 187.916us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 187.559us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 302.000s 14032.278us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 20.000s 3489.760us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 70332253053489288786559546215414076140746597412188780026759464718865675812781 144
UVM_INFO @ 3489759707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_lo_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 54447359283622694811220613899292556459803168445593613520908328093179538460028 113
UVM_INFO @ 20794875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---