Simulation Results: hmac

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.06 %
  • code
  • 95.95 %
  • assert
  • 96.96 %
  • func
  • 29.28 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 13.000s 1515.776us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 43.604us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 64.919us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 12.000s 1954.870us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 66.040us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 28.067us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 64.919us 1 1 100.00
hmac_csr_aliasing 3.000s 66.040us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 53.000s 22091.644us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 47.000s 2994.552us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 10.000s 1909.941us 1 1 100.00
hmac_test_sha384_vectors 21.000s 420.871us 1 1 100.00
hmac_test_sha512_vectors 382.000s 15540.225us 1 1 100.00
hmac_test_hmac256_vectors 12.000s 749.496us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 1882.328us 1 1 100.00
hmac_test_hmac512_vectors 13.000s 449.100us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 21.000s 3882.823us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 245.000s 8691.891us 1 1 100.00
error 1 1 100.00
hmac_error 54.000s 3402.567us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 106.000s 22074.770us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 13.000s 1515.776us 1 1 100.00
hmac_long_msg 53.000s 22091.644us 1 1 100.00
hmac_back_pressure 47.000s 2994.552us 1 1 100.00
hmac_datapath_stress 245.000s 8691.891us 1 1 100.00
hmac_burst_wr 21.000s 3882.823us 1 1 100.00
hmac_stress_all 44.000s 14936.605us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 13.000s 1515.776us 1 1 100.00
hmac_long_msg 53.000s 22091.644us 1 1 100.00
hmac_back_pressure 47.000s 2994.552us 1 1 100.00
hmac_datapath_stress 245.000s 8691.891us 1 1 100.00
hmac_wipe_secret 106.000s 22074.770us 1 1 100.00
hmac_test_sha256_vectors 10.000s 1909.941us 1 1 100.00
hmac_test_sha384_vectors 21.000s 420.871us 1 1 100.00
hmac_test_sha512_vectors 382.000s 15540.225us 1 1 100.00
hmac_test_hmac256_vectors 12.000s 749.496us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 1882.328us 1 1 100.00
hmac_test_hmac512_vectors 13.000s 449.100us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 13.000s 1515.776us 1 1 100.00
hmac_long_msg 53.000s 22091.644us 1 1 100.00
hmac_back_pressure 47.000s 2994.552us 1 1 100.00
hmac_datapath_stress 245.000s 8691.891us 1 1 100.00
hmac_burst_wr 21.000s 3882.823us 1 1 100.00
hmac_error 54.000s 3402.567us 1 1 100.00
hmac_wipe_secret 106.000s 22074.770us 1 1 100.00
hmac_test_sha256_vectors 10.000s 1909.941us 1 1 100.00
hmac_test_sha384_vectors 21.000s 420.871us 1 1 100.00
hmac_test_sha512_vectors 382.000s 15540.225us 1 1 100.00
hmac_test_hmac256_vectors 12.000s 749.496us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 1882.328us 1 1 100.00
hmac_test_hmac512_vectors 13.000s 449.100us 1 1 100.00
hmac_stress_all 44.000s 14936.605us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 44.000s 14936.605us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 15.386us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 19.893us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.000s 937.322us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.000s 937.322us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 43.604us 1 1 100.00
hmac_csr_rw 2.000s 64.919us 1 1 100.00
hmac_csr_aliasing 3.000s 66.040us 1 1 100.00
hmac_same_csr_outstanding 2.000s 133.282us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 43.604us 1 1 100.00
hmac_csr_rw 2.000s 64.919us 1 1 100.00
hmac_csr_aliasing 3.000s 66.040us 1 1 100.00
hmac_same_csr_outstanding 2.000s 133.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 76.084us 1 1 100.00
hmac_tl_intg_err 2.000s 189.340us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 189.340us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 13.000s 1515.776us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 211.705us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 116.000s 4903.855us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.000s 47.022us 1 1 100.00