Simulation Results

Simulation Results: i2c

27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.67 %

code
85.61 %

assert
96.83 %

func
80.56 %

block
95.98 %

line
95.29 %

branch
92.78 %

toggle
72.35 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	43.000s	8425.653us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	12.000s	2455.326us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	24.983us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	2.000s	23.124us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.000s	168.244us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	237.911us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	61.607us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	2.000s	23.124us	1	1	100.00
	i2c_csr_aliasing	2.000s	237.911us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	246.620us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	207.000s	7273.910us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	75.000s	944.201us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	18.742us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3601.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	652.000s	1818.116us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	131.871us	1	1	100.00
	i2c_host_fifo_fmt_empty	14.000s	5419.269us	1	1	100.00
	i2c_host_fifo_reset_rx	3.000s	149.203us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	854.000s	2467.866us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	12.000s	756.825us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	2.000s	308.966us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.000s	1514.816us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.000s	615.145us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	47.000s	2390.781us	1	1	100.00
	i2c_target_intr_smoke	7.000s	2442.053us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	3.000s	394.997us	1	1	100.00
	i2c_target_fifo_reset_tx	1.000s	1189.914us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	10.000s	16741.832us	1	1	100.00
	i2c_target_stress_rd	47.000s	2390.781us	1	1	100.00
	i2c_target_intr_stress_wr	5.000s	15857.701us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	7.000s	5881.257us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	696.000s	3236.526us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	7.000s	4012.674us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	3.000s	1317.080us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.000s	1515.661us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	479.823us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	75.000s	944.201us	1	1	100.00
	i2c_host_perf_precise	2.000s	42.634us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	12.000s	756.825us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.000s	199.642us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	5.000s	1808.687us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	2326.964us	1	1	100.00
	i2c_target_nack_txstretch	2.000s	514.111us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	6.000s	4281.928us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	704.555us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	17.015us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	22.270us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	74.524us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	74.524us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	24.983us	1	1	100.00
	i2c_csr_rw	2.000s	23.124us	1	1	100.00
	i2c_csr_aliasing	2.000s	237.911us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	34.651us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	24.983us	1	1	100.00
	i2c_csr_rw	2.000s	23.124us	1	1	100.00
	i2c_csr_aliasing	2.000s	237.911us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	34.651us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	176.417us	1	1	100.00
	i2c_sec_cm	1.000s	237.770us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	176.417us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	7.000s	681.257us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	66.254us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	12.000s	1350.638us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				2 test runs
	i2c_host_fifo_watermark	30529163855518004743004084058571641509056886824235100811834069718792301018349	None
	i2c_target_stress_all	108215981591260200582664263555852736074686373327889187492180363584126728471515	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	72862480166101876562473453368822545064259136629767818885353626532527417876030	97	UVM_INFO @ 246619889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	69773684178952402905384019846964818958598210680224534234154296091472090649483	135	UVM_INFO @ 7273910026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	69163578942460191725222667712016156197090566192779034975460262375779401915620	93	UVM_INFO @ 681257284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	89871797155097151726302496695390129332883212486892347769415530890557784382999	95	UVM_INFO @ 1350637752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	39564865473238923502620784588810984217702590030262906624316714209008683055037	93	UVM_INFO @ 1514815838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	31367217827348636749327285340464606185388680805336753760166988612226658352969	87	UVM_INFO @ 66254058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---