| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| keymgr_dpe_smoke | 14.000s | 1124.591us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 2.000s | 39.671us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_rw | 2.000s | 14.728us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_bit_bash | 5.000s | 9321.699us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_aliasing | 5.000s | 342.794us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_mem_rw_with_rand_reset | 2.000s | 161.259us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| keymgr_dpe_csr_rw | 2.000s | 14.728us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_aliasing | 5.000s | 342.794us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| intr_test | 1 | 1 | 100.00 | |||
| keymgr_dpe_intr_test | 2.000s | 38.120us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| keymgr_dpe_alert_test | 2.000s | 75.350us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| keymgr_dpe_tl_errors | 4.000s | 144.389us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| keymgr_dpe_tl_errors | 4.000s | 144.389us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 2.000s | 39.671us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_rw | 2.000s | 14.728us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_aliasing | 5.000s | 342.794us | 1 | 1 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 2.000s | 58.813us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 2.000s | 39.671us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_rw | 2.000s | 14.728us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_aliasing | 5.000s | 342.794us | 1 | 1 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 2.000s | 58.813us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| keymgr_dpe_sec_cm | 6.000s | 679.582us | 1 | 1 | 100.00 | |
| keymgr_dpe_tl_intg_err | 5.000s | 801.318us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 2.000s | 401.691us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 2.000s | 401.691us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 2.000s | 401.691us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 2.000s | 401.691us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors_with_csr_rw | 5.000s | 112.610us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| keymgr_dpe_sec_cm | 6.000s | 679.582us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| keymgr_dpe_sec_cm | 6.000s | 679.582us | 1 | 1 | 100.00 | |