Simulation Results: lc_ctrl/volatile_unlock_disabled

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.90 %
  • code
  • 92.55 %
  • assert
  • 96.69 %
  • func
  • 86.45 %
  • block
  • 96.66 %
  • line
  • 97.35 %
  • branch
  • 91.49 %
  • toggle
  • 86.12 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 378.153us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 17.409us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 60.685us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 221.787us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 24.399us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 234.522us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 60.685us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 24.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 293.886us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.000s 337.164us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 14.489us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 453.636us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 3.000s 265.786us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.000s 436.968us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 3.000s 265.786us 1 1 100.00
lc_ctrl_prog_failure 2.000s 453.636us 1 1 100.00
lc_ctrl_errors 7.000s 436.968us 1 1 100.00
lc_ctrl_security_escalation 5.000s 1357.099us 1 1 100.00
lc_ctrl_jtag_state_failure 20.000s 2821.709us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 483.761us 1 1 100.00
lc_ctrl_jtag_errors 14.000s 2276.056us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.000s 2403.925us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.000s 482.070us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 483.761us 1 1 100.00
lc_ctrl_jtag_errors 14.000s 2276.056us 1 1 100.00
lc_ctrl_jtag_access 7.000s 854.467us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.000s 4932.874us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 393.410us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 37.443us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.000s 1050.745us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 3675.304us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 33.504us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.000s 153.702us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 114.344us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.000s 1380.250us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 27.612us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 22.000s 5275.708us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 78.679us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 29.571us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 29.571us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.409us 1 1 100.00
lc_ctrl_csr_rw 2.000s 60.685us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 24.399us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 73.952us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.409us 1 1 100.00
lc_ctrl_csr_rw 2.000s 60.685us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 24.399us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 73.952us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 243.370us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 75.898us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 75.898us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.000s 337.164us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 265.786us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.370us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 265.786us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.370us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 3.000s 265.786us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.370us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 3.000s 265.786us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.370us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 265.786us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.370us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 265.786us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.370us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 265.786us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.370us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 3.000s 265.786us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.370us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 1357.099us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 293.886us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.000s 482.070us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 1475.833us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 1475.833us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 483.032us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 1617.410us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 1617.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 12.000s 2273.280us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 23377199727235960579826650551384309112997161433451059126587049939399779821227 1036
UVM_INFO @ 2273280180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---