Simulation Results: lc_ctrl/volatile_unlock_enabled

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.16 %
  • code
  • 93.80 %
  • assert
  • 96.54 %
  • func
  • 86.13 %
  • block
  • 96.98 %
  • line
  • 97.57 %
  • branch
  • 92.33 %
  • toggle
  • 87.66 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 30.855us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 17.977us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 92.068us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 23.962us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 16.566us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 25.811us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 92.068us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 16.566us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 1005.725us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 200.660us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 141.304us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 281.193us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 296.438us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.000s 680.941us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 296.438us 1 1 100.00
lc_ctrl_prog_failure 3.000s 281.193us 1 1 100.00
lc_ctrl_errors 4.000s 680.941us 1 1 100.00
lc_ctrl_security_escalation 4.000s 271.544us 1 1 100.00
lc_ctrl_jtag_state_failure 14.000s 10633.895us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 670.051us 1 1 100.00
lc_ctrl_jtag_errors 10.000s 2935.295us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.000s 1333.066us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.000s 3241.654us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 670.051us 1 1 100.00
lc_ctrl_jtag_errors 10.000s 2935.295us 1 1 100.00
lc_ctrl_jtag_access 5.000s 6084.634us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 4333.103us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 87.546us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 112.402us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.000s 3592.570us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.000s 3829.467us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 256.649us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 232.080us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 18.803us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 2114.931us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 79.899us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 42.000s 124324.971us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 181.654us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 170.638us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 170.638us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.977us 1 1 100.00
lc_ctrl_csr_rw 2.000s 92.068us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 16.566us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 146.447us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.977us 1 1 100.00
lc_ctrl_csr_rw 2.000s 92.068us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 16.566us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 146.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 2.000s 127.438us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 52.968us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 52.968us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 200.660us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 296.438us 1 1 100.00
lc_ctrl_sec_cm 2.000s 127.438us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 296.438us 1 1 100.00
lc_ctrl_sec_cm 2.000s 127.438us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 296.438us 1 1 100.00
lc_ctrl_sec_cm 2.000s 127.438us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 296.438us 1 1 100.00
lc_ctrl_sec_cm 2.000s 127.438us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 296.438us 1 1 100.00
lc_ctrl_sec_cm 2.000s 127.438us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 296.438us 1 1 100.00
lc_ctrl_sec_cm 2.000s 127.438us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 296.438us 1 1 100.00
lc_ctrl_sec_cm 2.000s 127.438us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 296.438us 1 1 100.00
lc_ctrl_sec_cm 2.000s 127.438us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 271.544us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 1005.725us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.000s 3241.654us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 393.089us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 393.089us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.000s 271.171us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 3001.129us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 3001.129us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 9.000s 2940.696us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 95509738301221560509333666806061204122189432403689559822957703154783473206377 1374
UVM_INFO @ 2940695759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---