Simulation Results: mbx

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.10 %
  • code
  • 89.16 %
  • assert
  • 97.62 %
  • func
  • 74.51 %
  • block
  • 96.88 %
  • line
  • 96.71 %
  • branch
  • 91.89 %
  • toggle
  • 78.87 %
Validation stages
V1
83.33%
V2
72.73%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 18.000s 1073.251us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 28.941us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 82.552us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 2.000s 100.174us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 21.729us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 0.971us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 82.552us 1 1 100.00
mbx_csr_aliasing 1.000s 21.729us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 2.000s 16.445us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 2.000s 66.878us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 21.000s 2628.400us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 8.000s 1480.525us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 30.041us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 16.997us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 3.796us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 3.796us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 28.941us 1 1 100.00
mbx_csr_rw 1.000s 82.552us 1 1 100.00
mbx_csr_aliasing 1.000s 21.729us 1 1 100.00
mbx_same_csr_outstanding 2.000s 29.308us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 28.941us 1 1 100.00
mbx_csr_rw 1.000s 82.552us 1 1 100.00
mbx_csr_aliasing 1.000s 21.729us 1 1 100.00
mbx_same_csr_outstanding 2.000s 29.308us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 209.093us 1 1 100.00
mbx_sec_cm 1.000s 30.717us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 96908873203194951859165820894705840486009921716869442978280589503463618126592 85
TL item was: req: (cip_tl_seq_item@18401) { a_addr: 'h482b6294 a_data: 'h44c17b4f a_mask: 'h1 a_size: 'h0 a_param: 'h0 a_source: 'h68 a_opcode: 'h0 a_user: 'h2788b d_param: 'h0 d_source: 'h68 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 3796344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 16431904061435913409173713239692984929327842362176140527884350562208381280271 86
TL item was: req: (cip_tl_seq_item@19494) { a_addr: 'hdf91310 a_data: 'h8d11ed8b a_mask: 'h9 a_size: 'h2 a_param: 'h0 a_source: 'h99 a_opcode: 'h1 a_user: 'h24e25 d_param: 'h0 d_source: 'h99 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 971173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed 1 test run
mbx_stress 75900359615367938869170034274341794279191289647924678752685793095934250354687 176
UVM_ERROR @ 16445141 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 16445141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_stress_zero_delays 112206108414813958958631486941457457970246596205082823440749967462564645615046 510
UVM_INFO @ 66878270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---