| V1 |
|
100.00% |
| V2 |
|
92.86% |
| V2S |
|
92.00% |
| V3 |
|
0.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| otbn_smoke | 10.000s | 38.624us | 1 | 1 | 100.00 | |
| single_binary | 1 | 1 | 100.00 | |||
| otbn_single | 8.000s | 17.010us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otbn_csr_hw_reset | 4.000s | 30.190us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otbn_csr_rw | 4.000s | 50.499us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otbn_csr_bit_bash | 6.000s | 85.085us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otbn_csr_aliasing | 4.000s | 133.269us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 6.000s | 97.317us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otbn_csr_rw | 4.000s | 50.499us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 4.000s | 133.269us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otbn_mem_walk | 48.000s | 752.508us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otbn_mem_partial_access | 52.000s | 12592.104us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 1 | 1 | 100.00 | |||
| otbn_reset | 33.000s | 192.672us | 1 | 1 | 100.00 | |
| multi_error | 0 | 1 | 0.00 | |||
| otbn_multi_err | 46.000s | 1026.708us | 0 | 1 | 0.00 | |
| back_to_back | 1 | 1 | 100.00 | |||
| otbn_multi | 237.000s | 1173.629us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| otbn_stress_all | 15.000s | 42.152us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| otbn_escalate | 11.000s | 45.425us | 1 | 1 | 100.00 | |
| zero_state_err_urnd | 1 | 1 | 100.00 | |||
| otbn_zero_state_err_urnd | 5.000s | 19.969us | 1 | 1 | 100.00 | |
| sw_errs_fatal_chk | 1 | 1 | 100.00 | |||
| otbn_sw_errs_fatal_chk | 11.000s | 23.288us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| otbn_alert_test | 4.000s | 92.646us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otbn_intr_test | 4.000s | 18.673us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 8.000s | 78.736us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 8.000s | 78.736us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 4.000s | 30.190us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 4.000s | 50.499us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 4.000s | 133.269us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 5.000s | 44.867us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 4.000s | 30.190us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 4.000s | 50.499us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 4.000s | 133.269us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 5.000s | 44.867us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 2 | 2 | 100.00 | |||
| otbn_imem_err | 8.000s | 58.617us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 8.000s | 35.368us | 1 | 1 | 100.00 | |
| internal_integrity | 4 | 4 | 100.00 | |||
| otbn_alu_bignum_mod_err | 13.000s | 123.310us | 1 | 1 | 100.00 | |
| otbn_controller_ispr_rdata_err | 8.000s | 30.352us | 1 | 1 | 100.00 | |
| otbn_mac_bignum_acc_err | 6.000s | 292.365us | 1 | 1 | 100.00 | |
| otbn_urnd_err | 5.000s | 51.274us | 1 | 1 | 100.00 | |
| illegal_bus_access | 1 | 1 | 100.00 | |||
| otbn_illegal_mem_acc | 7.000s | 63.000us | 1 | 1 | 100.00 | |
| otbn_mem_gnt_acc_err | 1 | 1 | 100.00 | |||
| otbn_mem_gnt_acc_err | 6.000s | 14.511us | 1 | 1 | 100.00 | |
| otbn_non_sec_partial_wipe | 0 | 1 | 0.00 | |||
| otbn_partial_wipe | 1.237s | 0.000us | 0 | 1 | 0.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| otbn_sec_cm | 308.000s | 12117.147us | 1 | 1 | 100.00 | |
| otbn_tl_intg_err | 13.000s | 180.627us | 1 | 1 | 100.00 | |
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| otbn_passthru_mem_tl_intg_err | 44.000s | 195.037us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 308.000s | 12117.147us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 308.000s | 12117.147us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 10.000s | 38.624us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_dmem_err | 8.000s | 35.368us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_imem_err | 8.000s | 58.617us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otbn_tl_intg_err | 13.000s | 180.627us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 11.000s | 45.425us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_local_esc | 5 | 5 | 100.00 | |||
| otbn_imem_err | 8.000s | 58.617us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 8.000s | 35.368us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 5.000s | 19.969us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 7.000s | 63.000us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 308.000s | 12117.147us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 308.000s | 12117.147us | 1 | 1 | 100.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 8.000s | 17.010us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 5 | 5 | 100.00 | |||
| otbn_imem_err | 8.000s | 58.617us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 8.000s | 35.368us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 5.000s | 19.969us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 7.000s | 63.000us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 308.000s | 12117.147us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 308.000s | 12117.147us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 11.000s | 45.425us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 5 | 5 | 100.00 | |||
| otbn_imem_err | 8.000s | 58.617us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 8.000s | 35.368us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 5.000s | 19.969us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 7.000s | 63.000us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 308.000s | 12117.147us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 308.000s | 12117.147us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sca | 1 | 1 | 100.00 | |||
| otbn_single | 8.000s | 17.010us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_redun | 1 | 1 | 100.00 | |||
| otbn_ctrl_redun | 6.000s | 58.908us | 1 | 1 | 100.00 | |
| sec_cm_pc_ctrl_flow_redun | 1 | 1 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 7.000s | 36.573us | 1 | 1 | 100.00 | |
| sec_cm_rnd_bus_consistency | 0 | 1 | 0.00 | |||
| otbn_rnd_sec_cm | 14.000s | 96.904us | 0 | 1 | 0.00 | |
| sec_cm_rnd_rng_digest | 0 | 1 | 0.00 | |||
| otbn_rnd_sec_cm | 14.000s | 96.904us | 0 | 1 | 0.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_base_intg_err | 10.000s | 25.558us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 308.000s | 12117.147us | 1 | 1 | 100.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 308.000s | 12117.147us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_bignum_intg_err | 9.000s | 199.612us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 308.000s | 12117.147us | 1 | 1 | 100.00 | |
| sec_cm_loop_stack_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 308.000s | 12117.147us | 1 | 1 | 100.00 | |
| sec_cm_loop_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 13.000s | 125.348us | 1 | 1 | 100.00 | |
| sec_cm_call_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 13.000s | 125.348us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 1 | 1 | 100.00 | |||
| otbn_sec_wipe_err | 5.000s | 35.728us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 8.000s | 17.010us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 8.000s | 17.010us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 8.000s | 17.010us | 1 | 1 | 100.00 | |
| sec_cm_write_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_multi | 237.000s | 1173.629us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_count | 1 | 1 | 100.00 | |||
| otbn_single | 8.000s | 17.010us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_sca | 1 | 1 | 100.00 | |||
| otbn_single | 8.000s | 17.010us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sw_noaccess | 1 | 1 | 100.00 | |||
| otbn_sw_no_acc | 8.000s | 17.061us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 8.000s | 17.010us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 308.000s | 12117.147us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| otbn_stress_all_with_rand_reset | 175.000s | 2177.718us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| otbn_smoke_vectorized | 7.000s | 19.766us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. | 2 test runs | |||
| otbn_multi_err | 62055832580030935265397037807450689627080665447172719287257040633419188714242 | 379 |
UVM_INFO @ 1026708110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_rnd_sec_cm | 33553061443156765088285480249977834968117753371837836221321646465153043624340 | 105 |
UVM_INFO @ 96903957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| otbn_stress_all_with_rand_reset | 33380112439219593642556849591446731017411856344527828686531348120084461892118 | 480 |
UVM_INFO @ 2177717652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 1 test run | |||
| otbn_partial_wipe | 97746672542647987457309437698071951710080640483901783605575722659498295959648 | None |
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
|
|