Simulation Results: otp_ctrl

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.70 %
  • code
  • 71.14 %
  • assert
  • 93.76 %
  • func
  • 53.21 %
  • line
  • 87.47 %
  • branch
  • 83.79 %
  • cond
  • 85.58 %
  • toggle
  • 60.81 %
  • FSM
  • 38.05 %
Validation stages
V1
88.89%
V2
60.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.200s 853.801us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 12.800s 5252.188us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.330s 1917.091us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.640s 52.922us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.650s 401.502us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 7.270s 3146.800us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.720s 501.002us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.640s 52.922us 1 1 100.00
otp_ctrl_csr_aliasing 7.270s 3146.800us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.380s 42.076us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.370s 43.986us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 100.670s 5804.455us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.340s 635.022us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 9.790s 3923.497us 0 1 0.00
otp_ctrl_check_fail 3.750s 211.647us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.190s 501.149us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 3.940s 505.411us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 16.580s 3915.222us 1 1 100.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 8.760s 361.619us 0 1 0.00
otp_ctrl_parallel_lc_esc 3.600s 765.220us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 61.420s 34373.275us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 14.670s 2811.224us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 2.320s 112.403us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 3.520s 439.963us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.520s 85.094us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.980s 78.737us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.020s 170.802us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.020s 170.802us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.330s 1917.091us 1 1 100.00
otp_ctrl_csr_rw 2.640s 52.922us 1 1 100.00
otp_ctrl_csr_aliasing 7.270s 3146.800us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.470s 369.665us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.330s 1917.091us 1 1 100.00
otp_ctrl_csr_rw 2.640s 52.922us 1 1 100.00
otp_ctrl_csr_aliasing 7.270s 3146.800us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.470s 369.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
otp_ctrl_tl_intg_err 11.850s 3161.625us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 11.850s 3161.625us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 12.800s 5252.188us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 12.800s 5252.188us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.600s 765.220us 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.600s 765.220us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.600s 765.220us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.600s 765.220us 1 1 100.00
otp_ctrl_macro_errs 14.670s 2811.224us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.600s 765.220us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.600s 765.220us 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.600s 765.220us 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.600s 765.220us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.600s 765.220us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.600s 765.220us 1 1 100.00
otp_ctrl_macro_errs 14.670s 2811.224us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.600s 765.220us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.600s 765.220us 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.340s 635.022us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.750s 211.647us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 3.940s 505.411us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 3.940s 505.411us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 3.940s 505.411us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 3.940s 505.411us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 3.940s 505.411us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 12.800s 5252.188us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 3.940s 505.411us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 12.800s 5252.188us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 295.640s 72117.796us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.190s 501.149us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 12.800s 5252.188us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 12.800s 5252.188us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 14.670s 2811.224us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 88.390s 69091.257us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 15.390s 1985.088us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 5 test runs
otp_ctrl_background_chks 78170771088815654052797259342117260692991097909624027556436293826760652393562 10503
UVM_INFO @ 3923496565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 85100987603939008253375684283507680084410958390874671122109630988209387397632 2396
UVM_INFO @ 505411061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 26298821524648659159427345175070737500029152833206225483083456041284708945209 958
UVM_INFO @ 112403216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 14356662761886439551507188106028784453513608758499498903988980594136677182017 1875
UVM_INFO @ 1985088117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 38837577604911827538635481216517357400511756982130425147462244005800587539251 3037
UVM_INFO @ 439962840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 2 test runs
otp_ctrl_check_fail 75087618737435446998833234343665785829748795238775587846985641917677811588141 2610
UVM_INFO @ 211647257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 47566033772200043624913888770075652982539483284799412134265791043414811018753 9171
UVM_INFO @ 2811223650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_partition_walk 95830406553017032035112043033187023480027065623429172760231038782780353706219 160055
UVM_INFO @ 5804454548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 67419990892787823465673031516631127605628409286613635985940109410458977081358 89
UVM_INFO @ 69091257454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:964) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 1 test run
otp_ctrl_parallel_lc_req 12044258366765020686249250247382737698981699939263466202564222398851810287866 8467
UVM_INFO @ 361619356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 102413682002157773441137264672184248098203650494876327237536241171982765453857 91
UVM_INFO @ 501001798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---