Simulation Results: rstmgr

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.03 %
  • code
  • 99.35 %
  • assert
  • 98.35 %
  • func
  • 96.39 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.98 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.690s 71.336us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.920s 65.431us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.760s 38.322us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.460s 124.124us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.250s 53.149us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.980s 65.533us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.760s 38.322us 1 1 100.00
rstmgr_csr_aliasing 1.250s 53.149us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.640s 118.342us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.120s 48.616us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.090s 69.206us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 6.800s 803.936us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 6.800s 803.936us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 6.800s 803.936us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 6.800s 803.936us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 21.710s 3469.961us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.890s 48.105us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.990s 72.086us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.990s 72.086us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.920s 65.431us 1 1 100.00
rstmgr_csr_rw 0.760s 38.322us 1 1 100.00
rstmgr_csr_aliasing 1.250s 53.149us 1 1 100.00
rstmgr_same_csr_outstanding 1.010s 41.956us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.920s 65.431us 1 1 100.00
rstmgr_csr_rw 0.760s 38.322us 1 1 100.00
rstmgr_csr_aliasing 1.250s 53.149us 1 1 100.00
rstmgr_same_csr_outstanding 1.010s 41.956us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 30.010s 6893.055us 1 1 100.00
rstmgr_tl_intg_err 4.890s 718.254us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 30.010s 6893.055us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 30.010s 6893.055us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 4.890s 718.254us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.140s 67.091us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.870s 479.061us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.470s 291.417us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 30.010s 6893.055us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.760s 38.322us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.760s 38.322us 1 1 100.00