Simulation Results: rv_dm/use_dmi_interface

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.62 %
  • code
  • 83.25 %
  • assert
  • 96.74 %
  • func
  • 94.87 %
  • block
  • 93.24 %
  • line
  • 93.77 %
  • branch
  • 81.65 %
  • toggle
  • 77.24 %
  • FSM
  • 80.36 %
Validation stages
V1
96.30%
V2
73.91%
V2S
85.71%
V3
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 32.000s 887.906us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 38.000s 1066.119us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 29.000s 166.311us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 48.000s 26138.841us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 31.000s 285.193us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 44.000s 21840.701us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 38.000s 7103.812us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 40.000s 54765.502us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 40.000s 30428.166us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 33.000s 400.201us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 32.000s 910.714us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 31.000s 229.209us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 32.000s 303.098us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 31.000s 101.350us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 30.000s 637.672us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 31.000s 132.688us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 31.000s 467.169us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 33.000s 400.201us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 30.000s 219.615us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 33.000s 852.632us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 31.000s 229.209us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 30.000s 37.158us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 33.000s 60.183us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 33.000s 136.656us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 50.000s 4856.530us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 60.000s 3934.762us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 30.000s 167.701us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 60.000s 3934.762us 1 1 100.00
rv_dm_csr_rw 33.000s 136.656us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 31.000s 57.151us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 29.000s 187.955us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 32.000s 887.906us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 30.000s 585.426us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 31.000s 364.993us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 30.000s 406.241us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 32.000s 363.155us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 33.000s 1692.475us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 32.000s 259.870us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 35.000s 820.245us 0 1 0.00
sba_autoincrement 1 1 100.00
rv_dm_autoincr_sba_tl_access 53.000s 16929.350us 1 1 100.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 31.000s 679.952us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 37.000s 917.964us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 31.000s 315.316us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 33.000s 40.313us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 49.000s 12759.924us 1 1 100.00
rv_dm_tap_fsm_rand_reset 56.000s 13631.836us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 31.000s 376.042us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 30.000s 2028.319us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 30.000s 72.623us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 33.000s 821.994us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 33.000s 821.994us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 60.000s 3934.762us 1 1 100.00
rv_dm_csr_hw_reset 33.000s 60.183us 1 1 100.00
rv_dm_csr_rw 33.000s 136.656us 1 1 100.00
rv_dm_same_csr_outstanding 34.000s 2357.019us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 60.000s 3934.762us 1 1 100.00
rv_dm_csr_hw_reset 33.000s 60.183us 1 1 100.00
rv_dm_csr_rw 33.000s 136.656us 1 1 100.00
rv_dm_same_csr_outstanding 34.000s 2357.019us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 30.000s 650.556us 1 1 100.00
rv_dm_tl_intg_err 36.000s 2128.300us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 36.000s 2128.300us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 37.000s 917.964us 1 1 100.00
rv_dm_debug_disabled 30.000s 122.360us 0 1 0.00
sec_cm_lc_dft_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 37.000s 917.964us 1 1 100.00
rv_dm_debug_disabled 30.000s 122.360us 0 1 0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 32.000s 887.906us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 33.000s 535.013us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 30.000s 62.295us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 30.000s 62.295us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 33.000s 535.013us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rv_dm_stress_all_with_rand_reset 51.000s 2004.396us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 527.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared: 2 test runs
rv_dm_sba_tl_access 36880143332987085396702412035578250816202638160894051742960685258646449170602 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23869
rv_dm_bad_sba_tl_access 67698943648576174590246038227880277021260706487315367958977090580522828910897 105
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @10263
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*]) 2 test runs
rv_dm_mem_tl_access_resuming 110084045028484725816012270210142468202328702996743094291575024381317559841665 87
UVM_INFO @ 303098403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 88674356690402053792663491466115364163509621084148599303155815316393317344221 104
UVM_INFO @ 2028319151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp 1 test run
rv_dm_delayed_resp_sba_tl_access 71842483313942150116891656988097825030041662429834038089578794123035322560114 107
UVM_INFO @ 259870475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*]) 1 test run
rv_dm_hart_unavail 108037935831389309817127490609572488026771791601144930260117906696310505291132 87
UVM_INFO @ 40312632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 1 test run
rv_dm_jtag_dmi_debug_disabled 53940898233438398396704792681740494606076429381398369369974723160138181951452 87
UVM_INFO @ 679951775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_rv_dm_sva_*/rv_dm_enable_checker.sv,42): Assertion DebugRequestNeedsDebug_A has failed 1 test run
rv_dm_debug_disabled 104137096915986119042506105387195923709159943583124478760684857738681558847686 89
UVM_ERROR @ 122360245 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)
UVM_INFO @ 122360245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_dm_scanmode 81194587343437424150712196885741680459860369946990897855971359081216575639446 87
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---