Simulation Results: rv_timer

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.66 %
  • code
  • 90.45 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 109.111us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 24.193us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 29.347us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 4.000s 2580.302us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 34.520us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 90.723us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 29.347us 1 1 100.00
rv_timer_csr_aliasing 1.000s 34.520us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.000s 887.256us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.000s 45.933us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 140.000s 159993.964us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 140.000s 159993.964us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.000s 1913.006us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 42.208us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 13.260us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 837.807us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 837.807us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 24.193us 1 1 100.00
rv_timer_csr_rw 1.000s 29.347us 1 1 100.00
rv_timer_csr_aliasing 1.000s 34.520us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 80.334us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 24.193us 1 1 100.00
rv_timer_csr_rw 1.000s 29.347us 1 1 100.00
rv_timer_csr_aliasing 1.000s 34.520us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 80.334us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 262.976us 1 1 100.00
rv_timer_tl_intg_err 1.000s 293.976us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 293.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 66.953us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 48.418us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 10.000s 5275.204us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 71706703565427094758974227599837681189054490354592195369622249579321909827827 84
UVM_INFO @ 66952985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 69866928264148148312764011787920144769421761273092011617492450952585785097800 84
UVM_INFO @ 887256232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 46960949364914374486485944060692575802514306638589669131641073932548290200660 84
UVM_INFO @ 48417949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---