Simulation Results: spi_device/1r1w

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.19 %
  • code
  • 89.52 %
  • assert
  • 95.40 %
  • func
  • 67.66 %
  • block
  • 98.33 %
  • line
  • 98.75 %
  • branch
  • 96.98 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 36.000s 3322.261us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 18.200us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 97.862us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 31.000s 8797.175us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 21.000s 1270.648us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 5.000s 227.352us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 97.862us 1 1 100.00
spi_device_csr_aliasing 21.000s 1270.648us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 107.739us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 86.855us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.000s 34.553us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 2.770us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 13.841us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 23.072us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 23.072us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 7.000s 1073.492us 1 1 100.00
spi_device_tpm_sts_read 2.000s 77.736us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 13.000s 7163.386us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 26.000s 3991.110us 1 1 100.00
spi_device_flash_all 97.000s 29290.083us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 65.000s 22724.642us 1 1 100.00
spi_device_flash_all 97.000s 29290.083us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 65.000s 22724.642us 1 1 100.00
spi_device_flash_all 97.000s 29290.083us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 97.000s 29290.083us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 10.000s 9057.321us 1 1 100.00
spi_device_flash_all 97.000s 29290.083us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 10.000s 9057.321us 1 1 100.00
spi_device_flash_all 97.000s 29290.083us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 10.000s 9057.321us 1 1 100.00
spi_device_flash_all 97.000s 29290.083us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 10.000s 9057.321us 1 1 100.00
spi_device_flash_all 97.000s 29290.083us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 10.000s 9057.321us 1 1 100.00
spi_device_flash_all 97.000s 29290.083us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.000s 190.707us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 3.000s 588.525us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 3.000s 588.525us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 3.000s 588.525us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 19.000s 11695.871us 1 1 100.00
spi_device_read_buffer_direct 6.000s 192.154us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 3.000s 588.525us 1 1 100.00
spi_device_flash_all 97.000s 29290.083us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 97.000s 29290.083us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 97.000s 29290.083us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 8.000s 2501.234us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 8.000s 2501.234us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 117.000s 10276.066us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 36.000s 3322.261us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 349.000s 33209.328us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 449.000s 39429.654us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 13.668us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 51.986us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 91.971us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 91.971us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 18.200us 1 1 100.00
spi_device_csr_rw 3.000s 97.862us 1 1 100.00
spi_device_csr_aliasing 21.000s 1270.648us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 396.613us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 18.200us 1 1 100.00
spi_device_csr_rw 3.000s 97.862us 1 1 100.00
spi_device_csr_aliasing 21.000s 1270.648us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 396.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 71.891us 1 1 100.00
spi_device_tl_intg_err 22.000s 990.253us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 22.000s 990.253us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 96996910347705007257452921467671083760407676372337502791053854425850869328596 87
UVM_ERROR @ 2451781 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[961] not found within the scope .
UVM_ERROR @ 2451781 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[961] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 40304581232786632278522272061254625071270514733966766466096320647429985076301 85
UVM_ERROR @ 11535949 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe5 [11100101] vs 0x0 [0])
UVM_ERROR @ 11586949 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2eb [1011101011] vs 0x0 [0])
UVM_ERROR @ 11666949 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x248 [1001001000] vs 0x0 [0])
UVM_ERROR @ 11683949 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x32d [1100101101] vs 0x0 [0])