Simulation Results: sram_ctrl/main

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.82 %
  • code
  • 94.96 %
  • assert
  • 97.69 %
  • func
  • 91.80 %
  • block
  • 95.08 %
  • line
  • 95.64 %
  • branch
  • 92.37 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 351.561us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 39.118us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.436us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 178.940us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.611us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 718.994us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 18.436us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.611us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 233.000s 103175.860us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 79.000s 1542.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 21.000s 8838.054us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 104.000s 3472.419us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 147.000s 15144.992us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 50.000s 23202.056us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 40.000s 40800.518us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 27.000s 25430.979us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 738.406us 1 1 100.00
sram_ctrl_partial_access_b2b 138.000s 4767.407us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 3.000s 666.803us 0 1 0.00
sram_ctrl_throughput_w_partial_write 5.000s 688.334us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 7296.006us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 952.297us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 1766.416us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 200.000s 31918.392us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 49.530us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 1384.145us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 1384.145us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 39.118us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.436us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.611us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 14.770us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 39.118us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.436us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.611us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 14.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 7129.981us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1009.423us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 275.830us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1009.423us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 275.830us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 952.297us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 952.297us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.436us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 27.000s 25430.979us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 27.000s 25430.979us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 27.000s 25430.979us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 40.000s 40800.518us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 6.000s 703.670us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 7129.981us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 4460.866us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 351.561us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 351.561us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 27.000s 25430.979us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1009.423us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 40.000s 40800.518us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1009.423us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1009.423us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 351.561us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1009.423us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 15.000s 661.603us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 105274793970638995203546901378328641116355404009774146936100789746062947690169 86
UVM_INFO @ 666803409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 65296835002989311363234364148196924593636123132980521196036451370546842197137 86
UVM_INFO @ 688333792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 96211438908387910061577635594096085987957255356486409387452521917139683319264 86
UVM_INFO @ 7296005965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---