Simulation Results: sram_ctrl/ret

 
27/07/2026 19:40:31 DVSim: v1.50.0 sha: 8e97d97 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.69 %
  • code
  • 82.27 %
  • assert
  • 97.81 %
  • func
  • 95.00 %
  • block
  • 93.81 %
  • line
  • 94.91 %
  • branch
  • 89.64 %
  • toggle
  • 77.84 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 62.185us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 14.218us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.631us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 101.885us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.622us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 111.465us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 15.631us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.622us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 1489.222us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 341.381us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 9.000s 376.289us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 193.000s 4884.523us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 144.459us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 10.000s 1621.381us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 400.639us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 4.000s 1146.938us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 64.620us 1 1 100.00
sram_ctrl_partial_access_b2b 152.000s 48880.108us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 100.397us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 55.970us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 29.353us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1749.520us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 88.825us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 39.000s 8739.350us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 43.961us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 9.000s 110.516us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 9.000s 110.516us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.218us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.631us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.622us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 89.683us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.218us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.631us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.622us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 89.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 1890.721us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 2469.393us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 2299.713us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 2469.393us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 2299.713us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1749.520us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1749.520us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.631us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 4.000s 1146.938us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 4.000s 1146.938us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 4.000s 1146.938us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 400.639us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 105.868us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 1890.721us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 34.944us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 62.185us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 62.185us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 4.000s 1146.938us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 2469.393us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 400.639us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 2469.393us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 2469.393us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 62.185us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 2469.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 16.000s 819.744us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 40104945414643925992336891694043450133376700046007834804873343241964682988854 86
UVM_INFO @ 100397064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 88675269019761463335706985039753157577653166279080470936752604350899652761646 86
UVM_INFO @ 55969702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 38118300229831352053948329273809488781220386466395300571041544156749986224180 86
UVM_INFO @ 29352860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 113351569056964436622496797213986060121018255198211997309482681001223124456015 88
UVM_INFO @ 111465232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---