Simulation Results: ac_range_check

 
28/07/2026 19:40:30 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.96 %
  • code
  • 93.15 %
  • assert
  • 97.75 %
  • func
  • 57.98 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.27 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 27.000s 3038.087us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 45.000s 5644.069us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 63.583us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 100.819us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 21.000s 709.581us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 18.000s 18435.674us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 55.397us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 100.819us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 18435.674us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 47.555us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 25.000s 1550.376us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 103.000s 6067.720us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 24.546us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 56.971us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 419.487us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 419.487us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 63.583us 1 1 100.00
ac_range_check_csr_rw 2.000s 100.819us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 18435.674us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 252.237us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 63.583us 1 1 100.00
ac_range_check_csr_rw 2.000s 100.819us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 18435.674us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 252.237us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 3596.246us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 3596.246us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 3596.246us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 3596.246us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 52.000s 1475.312us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 39.451us 1 1 100.00
ac_range_check_tl_intg_err 7.000s 360.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 194.000s 4715.765us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 25.000s 6079.611us 1 1 100.00